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A Reconfigurable Application-specific Instruction-set Processor for Fast Fourier Transform Processing

Authors:
Hussain, W. ,  Chen, X. ,  Ascheid, G. ,  Nurmi , J.
Book Title:
24th IEEE International Conference on Application-specific Systems, Architectures and Processors
Pages:
p.p. 339-345
Date:
Jun. 2013
ISSN:
2160-0511
DOI:
10.1109/ASAP.2013.6567599
Language:
English
Abstract:
In this paper, we have presented a Reconfigurable Application-specific Instruction-set Processor (rASIP) that processes mixed-radix(2, 4) 64 and 128-point Fast Fourier Transform (FFT) algorithms while satisfying the partial execution-time requirements of IEEE-802.11n standard. The rASIP was designed by integrating a template-based Coarse-Grain Reconfigurable Array (CGRA) in the datapath of a simple Reduced Instruction-Set Computing (RISC) Processor. The instruction set of the RISC processor was extended to add special instructions to enable cycle-accurate processing by the CGRA. The rASIP is synthesized for Field Programmable Gate Arrays for the measurement of resource utilization and execution time. The postfit gate-level netlist of rASIP was simulated to estimate the power and energy consumption. Based on our measurements and estimates, we have studied the advantages of using rASIP in comparison with other systems.}, keywords={fast Fourier transforms;field programmable gate arrays;reduced instruction set computing;wireless LAN;CGRA;FFT;IEEE-802.11n standard;RISC processor;coarse-grain reconfigurable array;execution time;fast Fourier transform processing;field programmable gate arrays;mixed-radix;rASIP;reconfigurable application-specific instruction-set processor;reduced instruction-set computing;resource utilization;Arrays;Avatars;Context;Process control;Reduced instruction set computing;Registers;Resource management
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