Institute for Communication Technologies and Embedded Systems

A 2.78 mm² 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Borlenghi, F. ,  Witte, E. M. ,  Ascheid, G.Meyr, H. ,  Burg, A.
Book Title:
IEEE European Solid-State Circuits Conference (ESSCIRC)
Sep. 2012
Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the - to the best of our knowledge - first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65nm CMOS ASIC has a core area of 2.78 mm2. Its maximum throughput exceeds 1 Gbit/s, at less than 1nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.

Copyright © by IEEE
© 2024 IEEE.Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.