Copic, M., Leupers, R. and Ascheid, G.: Reducing Idle Time in Event-Triggered Software Execution via Runnable Migration and DPM-Aware Scheduling, in Integration, the VLSI Journal, Vol. 70, Elsevier, pp. 10-20, Jan. 2020, 10.1016/j.vlsi.2019.09.004
Führ (Onnebrink), G., Hallawa, A., Leupers, R., Ascheid, G. and Eusse, J. F.: Multi-objective optimisation of software application mappings on heterogeneous MPSoCs: TONPET versus R2-EMOA, in (Integration), Vol. 69, Elsevier, pp. 50-61, Nov. 2019, 10.1016/j.vlsi.2019.09.005
Führ (Onnebrink), G., Hamurcu, S., Pala, D., Grass, T., Leupers, R., Ascheid, G. and Eusse, J. F.: Automatic Energy-Minimised HW/SW Partitioning for FPGA-Accelerated MPSoCs, in (IEEE ESL), Vol. 11, No. 3, pp. 93-96, Sep. 2019, 10.1109/LES.2019.2901224 ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries, in 24th IEEE European Test Symposium (ETS'19), May. 2019, accepted for publication ©2019 IEEE
Šišejković, D., Merchant, F., Leupers, R., Ascheid, G. and Kegreiss, S.: Control-Lock: Securing Processor Cores Against Software-Controlled Hardware Trojans, in Great Lakes Symposium on VLSI (GLSVLSI'19), May. 2019, 10.1145/3299874.3317983 ©2019 IEEE
Prof. Ascheid received the Dipl.-Ing. and Dr.-Ing. (PhD) degrees from the Aachen University in 1977 and 1984. PhD research focused on synchronization algorithms for digital receivers and their implementation using digital signal processing. This work was complemented by measurement and analysis of the non-linear behaviour of phase locked loops in noise. After the PhD he worked as Sr. Researcher at the Aachen University , continuing the research on synchronization and working on various industry consulting projects for European and US based companies. During that time he co-authored (jointly with Dr. Meyr) the book "Synchronization in Digital Communications", published by Wiley in 1990.
In 1989 he started as a co-founder CADIS GmbH, a company which commercialized the COSSAP tool suite. As Managing Director he headed the design service activities of CADIS. Since 1994, when Synopsys acquired CADIS, he has held various positions at Synopsys. In my last position as a Sr. Director, he had worldwide responsibility for professional design services in Wireless and Broadband Communications with teams in Germany, France, India and US. Design projects mainly focused on system specification and implementation of the digital baseband section for wireless communication systems. Applications covered include Digital Video Broadcasting via Satellite, a proprietary satellite-based WAN, satellite-based mobile digital audio broadcasting (US), Spacecraft Transponder (for the European Space Agency, ESA), digital microwave (4-256 QAM), and cell phone standards like GSM/GPRS, EDGE, WCDMA(UMTS). Broadband designs were mainly in the areas of ATM and IP sec.
An essential part of the design projects was the development and advancement of the methodology required to effectively and successfully develop ASICs for complex wireless communication systems ("SoC"). Goal was a seamless design methodology from algorithm development through architecture optimization, HW/SW partitioning and implementation to correctly operating, competitive systems. A key element of the design process is standard compliance and verification. My responsibility also included Wireless and Broadband conformance verification products supporting this goal:
- Telecom Workbenches covering SDH, SONET, ATM and IP as well as
- Design Conformance Labs (based on Synopsys' tool CCSS) for GSM, EDGE, WCDMA, and TD-SCDMA
Teaching activities during that time include a seminar for professional engineers on "Advanced Digital Receivers for Wireless Communications", held jointly with H. Meyr, and an annual lecture on "Computer aided design of digital mobile receivers" at the Aachen University.