The number of components in multicore processors and modern System-on-Chips is increasing constantly. On-chip interconnection networks are used for communication due to their excellent scalability. Simulation is one important method for architectural exploration in the aforementioned systems. However, a detailed simulation of the interconnection network is too slow and does offers lavish accuracy. Therefore, more abstract transaction-level models offering better simulation speed are required.
Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.
Emoung others, these step must be done:
- Characterize router and network for different topologies under load
- Deduce latency model
- Implement model into TLM framework
- Benchmark against cycle-accurate model
- Describe power characteristics from RTL and deduce abstract model
- Evaluate models against state-of-the-art