Institute for Communication Technologies and Embedded Systems

Collaborative Project: NEUROSYS

Funding by „Mikroelektronik aus Deutschland - Innovationstreiber der Digitalisierung “ des Bundesministeriums für Bildung und Forschung (BMBF)

Software mapping tools for SoCs with neuromorphic accelerators

Neuromorphic accelerators in SoCs promise unprecedented energy efficiency and low latency for machine learning applications. Hence, their integration into many products in the mass market would be favorable. One significant roadblock is the lack of software development kits that enable risk-free and easy migration of existing ML applications to neuromorphic accelerators.

This project will contribute a set of prototypes for software development kits with the ultimate goal to map any ML workload to any neuromorphic accelerator. For this, we are building a compiler toolchain on top of MLIR. This integration into an industry-standard open-source compiler framework will facilitate easy mass-market adoption of neuromorphic ICs.

Analysis and defense of potential attack vectors on neuromorphic ICs

Cybersecurity is a ubiquitous and growing problem. The NeuroSys project faces these challenges head-on by investigating attack vectors and their defense on upcoming neuromorphic hardware before it has reached mass-market adoption.

In particular, the project is focused on hardware trojans. Hardware trojans are intentional, undesirable, and malicious modifications of an IC. The ever-increasing complexity of hardware development and manufacturing makes it easier for attackers to introduce trojans while also reducing the likelihood of detection.