Unfortunately, an exact evaluation of this probability is far too complex; both because of the high-dimensional integrals, and because of the enormous number of terms in the sum (for example, if the packet contains 1024 bits, then the first sum is over 21023 terms). Clearly, approximations must be made in order to enable a real-time implementation of the receiver in hardware.
Conventionally, the algorithm design has mainly been based on heuristical approaches. For example, in order to remove the high-dimensional integral over the channel matrices Hk, a channel estimation unit is used to obtain an estimate of the channel, based on some training data. Later stages of the algorithm are designed under the assumption of a perfectly known channel, and the estimate is treated as the true channel value.
Recently, the research focus has shifted towards more systematic receiver designs, especially sparked by the success of modern channel codes. Turbo and LDPC codes are two well-known examples, which enable virtually error-free communication at data rates close to the theoretical limit (Shannon capacity). The breakthrough in coding theory, starting in 1993, was the discovery of approximate decoding algorithms for these channel codes, which iteratively refine the estimate of parts of the codeword, based on the current knowledge about the other parts.
In modern receiver design, the idea behind iterative decoding is extended to cover the whole receiver: In each step, the estimate of a subset of the unknown random variables is updated, based on the current knowledge about the other variables. Picking up the example of channel estimation, instead of calculating a fixed channel estimate, an iterative receiver re-estimates the channel after decoding the data bits, this time based on the training symbols as well as the newly available knowledge about the data bits. The improved channel estimate in turn allows for a more reliable data decoding, and so on. Below is the structure of a typical triple-loop iterative receiver.
In this project, our research focus is on the implementation of the receiver components (e.g., the channel estimator and the MIMO detector), the communication between them, and the order in which they are activated (scheduling). Due to our tight interaction with the architecture research group at our institute (see “Flexible Architectures for Next-Generation Iterative MIMO Receivers”), the algorithmic complexity is of particular interest to us.