The performance and flexibility advantage of Coarse-grained Reconfigurable Architectures (CGRA) has been long established. However the increasing difficulty of designing such architectures is discouraging wide-spread adoption.
There are two main design challenges for CGRA: 1) Making full use of the available functional units of the array, implying better resource utilization, mapping and routing; and 2) existance of stable tools for modeling, programming simulation and debugging.
This project aims to address both, by adopting a new design concept while relying on high-level synthesis tools and description languages like LISA ADL.
Also, exploratory research is conducted in the direction of 3D silicon integration and functional architectures/reconfigurable architectures with functional programming interfaces.