Summer Semester 2018

Bachelor

Title
Lecturer
Type
Further Infos
P

Project Programming

Gerd Ascheid

Room: by arrangement

Contents

A basic communication system will be simulated, including packet-based communication, error detection and correction techniques (CRC, repetition codes), modulation (QPSK) and channel modeling (AWGN channel). An image is used as the information to be transmitted, so that the effects of the different parameters (different correction techniques, modulation encodings and channel SNRs) can be immediately visualized from a qualitative point of view; however, a quantitative measure is also given by computing the bit error rate. The simulator will include a backend, which runs the computationally-intensive tasks, and a GUI frontend, which allows the user to set parameters and see results coming out of the backend; both parts are implemented in C++ according to the object-oriented programming paradigm, with the help of Qt libraries for GUI and DBUS for inter-process communication.

Supervisors

S

Seminar Embedded System Design: Hardware Security

Rainer Leupers

Room: ICT cubes, Room 431

Contents

Assessment:

Students are expected to give a half an hour presentation at the end of semester. Reading materials will be provided.

 

Preliminary discussion and registration

18.04.2018 ICT cubes Kopernikusstr. 16

Contact:

Prof. Dr. Rainer Leupers, E-Mail:rainer.leupers(at)ice.rwth-aachen.de

Supervisors

V2
L2P

Foundations of Compiler Engineering

Rainer Leupers

Room: ICT cubes, Room 002

Contents

The course is tailored to students with interest to Software Engineering in general. To program a PC in a high level language, compilers are an irreplaceable tool, whose understanding builds the basis of every successful implementation of algorithms on a PC. Furthermore, the introduced problems and algorithms provide a wide background for the solution of problems on a PC.

In the domain of embedded systems, compilers have as outstanding role. This area comprises a much broader spectrum of architectures and requires at the same time much higher code quality (performance, code size etc.) than PCs do. Therefore, compilers are the key technology to develop programmable embedded systems, since they close the semantic gap between high level languages and machine languages.


Structure of the course:
Foundations of Compiler Engineering Advanced Compiler Engineering
 
  1. Introduction
  2. Lexical analysis
  3. Syntax analysis
  4. Semantic analysis
  5. Symbol tables
  6. Intermediate representations
  7. Control flow analysis
  8. Code selection
  9. Runtime system memory management
 
  1. Introduction
  2. Data flow analysis
  3. Intermediate code optimization
  4. Target processors
  5. Register allocation
  6. Scheduling
  7. Code optimization techniques
  8. Retargetable compilers

Assessment

There will be an oral examination on appointment.

Campus:

here

Supervisors

Tutorial for Foundations of Compiler Engineering
Ü1

Tutorial for Foundations of Compiler Engineering

Rainer Leupers

Contents

The materials for the tutorial will be available via L2P:

L2P for Foundations of Compiler Engineering

Contents updated weekly:

  • Commented foils of the lectures
  • Exercises
  • Solutions to the exercises of previous week

 

Supervisors

S

Tutorial for independent Scientific Work (semester theses, diploma- a. master thesis)

Gerd Ascheid
Rainer Leupers

Contents

Please find actual Study-/Diploma-/Master Thesis offers here.

Supervisors

P

Project Institute Project

Rainer Leupers

Room: ICT cubes, by arrangement

Contents

Microcontrollers from Texas Instruments (TI) provide a solution for a wide range of low power and portable applications. In this project we will program embedded software for a TI wireless chronos watch [1] combined with its RF access point receiver. The watch has embedded sensors that can be used to acquire data, including an on-board 3-axis accelerometer, pressure sensor, temperature sensor and a battery voltage sensor. The application proposed to be implemented is a portable trainer featuring the possibility for training configuration (e.g. weight, time, speed. distance). Necessary subtasks are (i) logging actual measured training data on the watch, (ii) lossless transmission of logged data to a workstation, and (iii) graphical visualization and data analysis.

Supervisors

Master

Title
Lecturer
Type
Further Infos
V2

Signal Processing in Multi-Antenna (MIMO) Communication Systems

Gerd Ascheid

Room: ICT cubes, Seminarraum 002, EG, Kopernikusstr. 16

Contents

  • Modelle für Fadingkanäle (Ein- und Mehrantennenfall)
  • Parameter von Fadingkanälen
  • Modulationsverfahren, OFDM
  • Konzepte für Mehr-Antennenübertragung
    • Strahlformung (Beamforming)
    • Räumliche Diversität
    • Räumliche Mehrfachübertragung (Spatial multiplexing)
    • Kanalschätzung
  • Wichtige Sätze der Matrixalgebra
  • Matrix-Modelle der Übertragung in Mehrantennen (MIMO) Systemen
  • Übertragungskapazitäten von MIMO Systemen, Diversität in MIMO Systemen
  • Optimale und suboptimale Datendetektion
  • Kanalschätzung
  • Iterative Empfänger

 

Supervisors

Signal Processing in Multi-Antenna (MIMO) Communication Systems
Ü1

Signal Processing in Multi-Antenna (MIMO) Communication Systems

Gerd Ascheid

Contents

- Modelle für Fadingkanäle (Ein- und Mehrantennenfall)

- Parameter von Fadingkanälen

- Modulationsverfahren, OFDM

- Konzepte für Mehr-Antennenübertragung

  • Strahlformung (Beamforming)
  • Räumliche Diversität
  • Räumliche Mehrfachübertragung (Spatial multiplexing)
  • Kanalschätzung

- Wichtige Sätze der Matrixalgebra

- Matrix-Modelle der Übertragung in Mehrantennen (MIMO) Systemen

- Übertragungskapazitäten von MIMO Systemen, Diversität in MIMO Systemen

- Optimale und suboptimale Datendetektion

- Kanalschätzung

- Iterative Empfänger

Supervisors

P

Entwurf digitaler integrierter Schaltkreise

Gerd Ascheid

Contents

Projekt "Entwurf digitaler integrierter Schaltkreise"


In diesem Projekt wird den Studenten der Entwurf und die Implementierung integrierter Schaltkreise beigebracht. Die Studenten lernen den kompletten Ablauf vom initialen Architektur-Konzept bis hin zum Modell der funktionsfähigen Hardware (Layout-Level) kennen.

Themen:

  •  Architekturentwurf (Register Transfer Level)
  •  VHDL-Implementierung RTL-Modell
  •  Gatelevel Synthesis mit Design Compiler
  •  Formale Verifikation mit Formality
  •  Simulation mit Modelsim und VCS (RTL und Gatelevel)
  •  Static Timing Analysis mit PrimeTime
  •  Layout mit Cadence Encounter (Foundation Flow)
  •  Power Estimation mit PrimeTime PX (Postsynthesis und Postlayout)
  •  Einfacher handgeschriebener VHDL-Testbench
  •  Erweiterter Testbench (aus dem Kaeslin-Buch)
  •  Ggf. UVM-basierter Testbench (Constrained Random Verification)
  •  SystemC/C++ Referenzmodell
  •  Ggf. Manueller Floorplan
  •  Linux/Shell Primer
  •  Subversion Primer


Der Kurs verwendet die Entwicklungsoberfläche DVT Eclipse.

Ablauf:

  1. Implementierung  eines einfachen Addierers (Entity, Datenpfad, Register) inklusive sehr einfachem Testbench (Component, Instanzierung sowie RTL-Simulation (Modelsim) und Synthese
  2. Implementierung eines Akkumulators (Mux, FSM) +Tb +Sim +Synthese +formale Verifikation
  3. Erweiterte Testbench anpassen
  4. Postsynthesis-Powerestimation (VCS, PrimeTime, ...)
  5. Layoutskripte anpassen und Layout erstellen sowie analysieren
  6. Postlayout-Powerestimation
  7. Wiederholung mit größerem Design


Das Projekt beginnt mit einer Einführung. Die Studenten erhalten mehrere aufeinander aufbauende Aufgaben, für deren Bearbeitung sie ausreichend Zeit bekommen. Beim Betreuungstermin werden die Lösungen besprochen, neue Themen eingeführt und dazu neue Aufgaben gestellt. Die Studenten können jederzeit werktags im Labor arbeiten. Sie erhalten einen eigenen Zugang zu unseren Computersystemen. Die Betreuer stehen ihnen für Fragen während der regelmäßigen Termine zur Verfügung. Eine vollständige Bearbeitung aller Aufgaben ist zum Erlangen des Leistungsnachweises erforderlich. Jeder Student arbeitet eigenständig (keine Gruppenarbeit) um den Lerneffekt zu maximieren. Die Veranstaltung und alle Unterlagen sind vollständig in Deutsch gehalten.

Termine
Die Veranstaltung beginnt in der zweiten Vorlesungswoche. Die weiteren Termine werden mit der Gruppe beim ersten Termin abgesprochen. Wir bevorzugen eine Art "Blockveranstaltung", also z.B. einige Tage Vollzeit, oder einen kompletten Tag pro Woche bis alle Aufgaben abgearbeitet sind. Anschließend bekommen die Studenten eine Projektaufgabe, die Sie eigenständig lösen um das gelernte Wissen zu verfestigen. Die Zeiteinteilung ist dann flexibel.

Voraussetzungen
Voraussetzung für die Teilnahme an dem Projekt ist der Bachelor-Abschluss. Bachelor-Studenten werden auch berücksichtigt, wenn sie 120 Credits erreicht haben. Insbesondere ist Grundwissen aus der Vorlesung "Grundgebiete der Informatik III" erforderlich.


Anmeldung
Mindestteilnehmerzahl 5, es werden maximal 10 Plätze angeboten.
Anmeldung per Email an icdesignlab@ice.rwth-aachen.de. Bitte gebt bei der Anmeldung Namen, Matrikelnummer, Semesterzahl, Studiengang, Email-Adresse und Telefonnummer an. Die Plätze werden nach der Eingangsreihenfolge der Emails vergeben. Für den Fall, dass alle Projektplätze vergeben sind, führen wir eine Warteliste.

Supervisors

V2

Algorithm Design for Digital Receivers

Gerd Ascheid

Room: ICT cubes, Seminarraum 002, EG Kopernikusstr. 16

Contents

The lecture will introduce the algorithm design of digital receivers, focussing on systematic design of synchronization algorithms. The first semester course "Detection and Estimation Theory" delivers the theoretical basis for this course. The lecture divides into the following parts of communication theory:

  • Modulation
  • General digital transceiver model
  • Digital receiver principles
  • Bandpass sampling
  • Optimum ML receiver for constant synchronization parameters
  • Systematic synthesis of synchronization algorithms based on the ML criteria
  • Digital algorithm for timing recovery
  • Timing adjustment by interpolation
  • Rate adaptation and modulation
  • Phase synchronization
  • Frequency estimation
  • Synchronizer performance analysis
  • Fading channel models
  • Optimum receiver for time varying channels

Assessment

There will be an oral examination of 20 minutes. Students are expected to show that they have fully acquired the topics of the lecture and that they are able to apply their theoretical knowledge and to transfer the techniques of calculus that were practised in the tutorial.

Language

English

Supervisors

Tutorial for Algorithm Design for Digital Receivers
Ü1

Tutorial for Algorithm Design for Digital Receivers

Gerd Ascheid

Contents

 

 

Supervisors

P

Lab: Entwurf digitaler Mobilfunkempfänger: Synchronisation und Detektion

Gerd Ascheid

Contents

Virtually all modern communication systems are based on digital data transmission, e.g. mobile cellular networks like GSM and UMTS, or broadcast systems like DVB. To detect the data in the receiver, the distortions that are introduced during the transmission must be estimated and corrected. Today, these tasks are mostly performed by digital signal processing.

In this lab course, you will learn to design digital receivers for realistic wireless systems, with a focus on signal processing aspects. You will start by modelling a very simple transmission system where the signal is only disturbed by additive noise. Realistic channels however introduce many other distortions into the signal, for example an unknown timing offset in the A/D converter. Therefore, in each lab you will adapt the receiver to more and more realistic channels by adding components like synchronization units and estimators for unknown channel parameters. In the end, you will have a receiver model that could be used in a realistic communication system.

All programming is done in MATLAB. However, programming experience in MATLAB is not required in order to attend this lab, as you will have the opportunity to become familiar with MATLAB during the course.

Organization

The lab takes place periodically in the summer term, and is offered as TÜ3 and TÜ4 course. 

The lab will be held in English. It takes place each Thursday between 3pm and 6pm in ICT cubes, Kopernikusstr. 16, Room 513

Supervisors

R. Leupers
A. Hoffmann
V2

Electronic Design Automation

Rainer Leupers
Andreas Hoffmann

Room: ICT cubes, Room 001

Contents

Diese Vorlesung wendet sich an Studenten mit Interesse im Bereich der Entwurfsautomatisierung digitaler Schaltungen und sogenannter "System on Chips (SoC)". Während Systeme ursprünglich aus einem Mikroprozessor- oder Mikrocontroller-IC und vielen anderen ICs bestanden, die auf einer Platine aufgelötet waren, geht heute der Trend dazu, möglichst alle Funktionen auf einem IC zu realisieren. Dabei werden digitale, analoge und Mixed-Signal-Funktionseinheiten integriert. Vorteile sind vor allem Kosteneinsparung und Miniaturisierung.

Im Rahmen der Vorlesung werden die Prinzipien des SoC Entwurfs erläutert - mit besondererem Fokus auf die Optimierung der Systemarchitektur und der eingebetteten Software. Dabei werden Entwurfsmethoden und Werkzeuge vorgestellt; dieses "System Level Design" wird im allgemeinen als die vielversprechendste Neuerung im Bereich der elektronischen Entwurfsautomatisierung gesehen und gehört zum Grundwerkzeug aller, die solche SoCs entwickeln wollen.

Struktur der Vorlesung:

  1. Eingebettete Systeme
  2. Mikroprozessoren
  3. Bus Systeme
  4. EDA I
  5. EDA II
  6. Electronic System Level
  7. Systembeschreibungssprachen
  8. System Level Design
  9. Exploration von Rechnerarchitekturen
  10. Entwicklung von eingebetteter Software

 

Prüfung
Mündliche Prüfungen n.V.

Supervisors

DiegoPala

Diego Pala

Email: diego.pala@ice.rwth-aachen.de

Tutorial for Electronic Design Automation
A. Hoffmann
R. Leupers
Ü1

Tutorial for Electronic Design Automation

Andreas Hoffmann
Rainer Leupers

Contents

 

 

Supervisors

DiegoPala

Diego Pala

Email: diego.pala@ice.rwth-aachen.de

V2
L2P

DSP Design Methodologies and Tools

Rainer Leupers

Room: ICT cubes, Room 002

Contents

  1. Introduction: Definition of embedded systems; design challenges; design methodologies
  2. System design: System design methodologies; requirements and specification
  3. Instruction sets: Basic classification of computer architecture; assembly language; examples of software assembly instruction-set
  4. Microprocessors: Various I/O mechanism; supervisor mode, exceptions, traps; co-processor
  5. Designing with microprocessors: Architectures and components (software, hardware); debugging; manufacturing testing
  6. Program design & analysis: Design patterns; representation of programs; assembling, linking
  7. VLSI implementation: Importance of VLSI; Moore's Law; VLSI design process
  8. RTL components: Shifters; adders; multipliers
  9. Architecture and chip design: Basics of register-transfer design; data path, controller; ASM chart; VHDL, Verilog overview
  10. CAD systems and algorithms: CAD systems; placement and routing; layout analysis

 

Assessment

There will be an oral examination of 20 minutes. Students are expected to show that they have acquired an understanding of the topics discussed during the lecture.

Campus

here

Supervisors

Tutorial for DSP Design Methodologies and Tools
Ü1

Tutorial for DSP Design Methodologies and Tools

Contents

 

 

Supervisors

S

Seminar Embedded System Design: Hardware Security

Rainer Leupers

Room: ICT cubes, Room 431

Contents

 

Assessment:

Students are expected to write a report of approximately 15 pages on an assigned topic, along with a half-hour presentation at the end of semester. Reading materials will be provided.

Preliminary discussion and registration

18.04.2018 ICT cubes Kopernikusstr. 16

Contact:

Prof. Dr. Rainer Leupers, E-Mail:rainer.leupers(at)ice.rwth-aachen.de

Supervisors

P

Projekt: Multicore Programming

Rainer Leupers

Contents

The trend towards multicore hardware architectures has a wide impact in virtually all domains of computing. For instance, multicore CPUs are already commodity in PCs, and many smartphones today employ 2 to 8 processor cores for application processing. The wide adoption of multicores also implies fundamental changes in software programming languages and tools. Well-proven sequential languages like C/C++ are not sufficient to capture software parallelism, while traditional compilers cannot utilize the processing power offered by modern multicores. Therefore, new parallel multicore programming concepts are currently under intensive discussion in academia and industry. This seminar will investigate current issues and future trends, including existing parallel programming approaches (e.g. MPI, OpenMP, OpenCL, Kahn Process Networks) and advanced software parallelization techniques for use in future compilers for multicores.

Preliminary discussion and application: 27.04.2017 18:00 ICT cubes 431

Supervisors

P

Project: Programmierung von Embedded-Multiprozessorsystemen

Rainer Leupers

Room: ICT cubes, Room 431

Contents

Multicore/Multiprocessor hardware platforms are finding widespread use in virtually all embedded ICT domains, including wireless communication, smartphones, automotive, computer vision, and many others. From a pure HW perspective, multicores are the key enablers for continued performance scaling in forthcoming compute-intensive applications, while keeping power/energy consumption and power density within reasonable limits. Systems-on-Chip (SoC´s) with dozens of programmable cores are becoming commodity today, and the ITRS roadmap predicts devices with 1000+ processor cores in the coming years. However, software development for multicores becomes a significant bottleneck. Migrating legacy application code or firmware as well as developing and debugging new software for highly parallel HW platforms causes a significant embedded SW productivity gap. This lab course provides hands-on experience in embedded multicore programming using advanced parallelizing compiler technology from Silexica, an ICE spin-off company.

Supervisors

G. Dartmann
A. Charlish
V2

Estimation, Information Fusion and Machine Learning - Cognitive Tools for Cyber-Physical Systems

Guido Dartmann
Alexander Charlish

Room: ICT cubes, Seminarraum 431, 4. OG, Kopernikusstr. 16

Contents

Supervisors

Further Information

Please find further information on lectures, tutorials and exams in Campus and L²P. When you sign in via Campus for lecture, you are automatically applied for L²P- eLearning  and eTeaching Portal.

News >> News >> News

ICE organizes a hardware security workshop at HiPEAC 2019

Along with Prof. Avi Mendelson from Technion, ICE's Prof. Rainer Leupers, Farhad Merchant

Publication of Third Edition of Handbook of Signal Processing Systems

Bhattacharyya, S.S.; Deprettere, E.F.; Leupers, R.; Takala, J. (Eds.), 3rd Edition., 2018-09-20,

Synopsys ASIP University Day 2018 - Europe

ASIP University Day 2018 took place at ICE on Wednesday, September 26th, 2018

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