Power-aware SW-task mapping for MPSoCs
The next generation of embedded systems and multiprocessor systems on chip (MPSoC) have to fulfil an increasing number of constraints such as sufficient performance for the ever increasing computational workloads. Also, heat issues and battery lifetime require tight power budgets. To tackle these requirements, heterogeneous MPSoCs with hundreds of cores are seen as a solution. They offer advantages of multiple different core types, different memory architectures and communication network topologies. Writing efficient SW optimised for performance and/or minimal power consumption bears huge challenges for such complex SoCs.
Here at the chair Software for Systems on Silicon (SSS), we look into the problem of co-optimising a given application for power and performance within the framework MPSoC Application Programming Studio (MAPS), which is commercially available for the industry provided by the spin-off Silexica.
Several key aspects are still under development. The following gives just a few examples.
- Improving the existing performance/power co-optimising heuristi
- Finding the optimal solution
- Taking the communication and memory power into account
- Developing a reliable and efficient power model
Other important steps required for reliable case studies would be to instrument and model the latest available heterogeneous MPSoC platform so that it can be used as reference for validating the mapping heuristic output.
Bachelor Thesis , Master Thesis, HiWis
Depending on the actual task, the following is essential:
- C/C++/Assembly programming
- Knowledge on embedded processor architectures
- Have some compiler background or experience
- Linux OS
In case of interest, please send me an email including your latest transcript of records.