Master and Bachelor theses offers

Bachelor Theses offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Bayesian machine learning on neuromorphic architectures

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Spiking neural networks can perform Bayesian inference in a highly accelerated form. Such models are adaptable and robust with respect to noise. An example is in hearing aids that adapt some of the acquisition parameters in real-time. The goal of this project is to enable Bayesian Machine Learning Algorithm on a neuromorphic compute architecture. The successful candidate will be given a chance to publish his findings (if relevant) to the scientific community through a peer-reviewed publication.

  • Development of an auto-tuner for efficient neural-network mapping for neuromorphic systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Part of any processor technology is an SDK, whose task it is (amongst others) to map a standard neural-network application, developed with Tensorflow, to a SoC. Therefore, the layers of the neural network must be assigned to cores in the NoC mesh of a  massive-many-core system. The goal of this thesis is to develop an auto-tuner to improve GML’s mapper. The task of the mapper is to assign layers of a neural network to cores in the NoC mesh of a massive-many-core system. The auto-tuner receives a set of optimization parameters, which are considered for optimizing the mapping.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a the aforementioned framework by a new in-house NoC model. Furthermore, a experiemental setup to assess the NoC's side channels must be implemented (including measurements in the lab).

  • Machine Learning for Security

    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.
    Supervisor: Dominik Šišejković

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • NoC design-space exploration for neuromorphic massive multicore systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to reflect a next-generation neuromorphic compute architecture. Thereby, the focus is on integrating a cycle-accurate, heavily parametrizable NoC model. This tool shall be subsequently used for NoC-architecture design-space exploration for massively-parallel neuromorphic computer architectures.

  • Pattern Reconstruction from Images for DNA-based Computing

    Description: In this task, you will invent a reconstruction algorithm to identify DNA-inputs using 2D and 3D videos of a micro-fluidic system. The microfluidic system will combine different DNA-snippets and a video is taken of the system. You will develop a reconstruction method (by linear programming, combinatorics of machine learning); the problem can be modeled as a string-matching algorithm.
    Supervisor: Dr.-Ing. Jan Moritz Joseph

  • SIEM Sensor für virtuelle Kraftwerke

    Tutors: Guido Dartmann, Gerd Ascheid

  • Tackling Avalanches in Spiking Neural Network Accelerators

    Description: In this master thesis, a standard spiking neural network is trained using Tensorflow. The avalanches are shown by means of software. Next, the amount and timing of avalanches are modeled mathematically. Furthermore, the software model is attached to a SystemC model of the on-chip network. The performance impact of avalanches is quantified. Finally, an architectural optimization is proposed to overcome performance limitations. 
    Supervisor: Dr.-Ing. Jan Moritz Joseph

Master Theses offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Bayesian machine learning on neuromorphic architectures

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Spiking neural networks can perform Bayesian inference in a highly accelerated form. Such models are adaptable and robust with respect to noise. An example is in hearing aids that adapt some of the acquisition parameters in real-time. The goal of this project is to enable Bayesian Machine Learning Algorithm on a neuromorphic compute architecture. The successful candidate will be given a chance to publish his findings (if relevant) to the scientific community through a peer-reviewed publication.

  • Development of an auto-tuner for efficient neural-network mapping for neuromorphic systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Part of any processor technology is an SDK, whose task it is (amongst others) to map a standard neural-network application, developed with Tensorflow, to a SoC. Therefore, the layers of the neural network must be assigned to cores in the NoC mesh of a  massive-many-core system. The goal of this thesis is to develop an auto-tuner to improve GML’s mapper. The task of the mapper is to assign layers of a neural network to cores in the NoC mesh of a massive-many-core system. The auto-tuner receives a set of optimization parameters, which are considered for optimizing the mapping.

  • Development of novel wireless transmission technologies

    Supervisor: Dr. Haris Kremo via jobs-dsp@ice.rwth-aachen.de
    Description:: Here at the Chair of Distributed Signal Processing (DSP) we have several master thesis offers to develop novel wireless transmission technologies (in particular physical-layer design) for modulation/demodulation, optimization, signal design, etc.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • Hardware Security: Secure Processor Design

    Supervisor: Lennart Reimann
    Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

  • High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a the aforementioned framework by a new in-house NoC model. Furthermore, a experiemental setup to assess the NoC's side channels must be implemented (including measurements in the lab).

  • Machine Learning for Security

    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.
    Supervisor: Dominik Šišejković

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • NoC design-space exploration for neuromorphic massive multicore systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to reflect a next-generation neuromorphic compute architecture. Thereby, the focus is on integrating a cycle-accurate, heavily parametrizable NoC model. This tool shall be subsequently used for NoC-architecture design-space exploration for massively-parallel neuromorphic computer architectures.

  • Pattern Reconstruction from Images for DNA-based Computing

    Description: In this task, you will invent a reconstruction algorithm to identify DNA-inputs using 2D and 3D videos of a micro-fluidic system. The microfluidic system will combine different DNA-snippets and a video is taken of the system. You will develop a reconstruction method (by linear programming, combinatorics of machine learning); the problem can be modeled as a string-matching algorithm.
    Supervisor: Dr.-Ing. Jan Moritz Joseph

  • Sensing Communications for 6G wireless systems

    Supervisor: Dr. Haris Kremo via jobs-dsp@ice.rwth-aachen.de
    Description:: At the Chair of Distributed Signal Processing (within the Institute for Communication Technologies and Embedded Systems) we have several offers for master thesis to develop novel technologies related to Sensing Communications in particular related to advancement of physical-layer signal processing and machine learning.

  • SIEM Sensor für virtuelle Kraftwerke

    Tutors: Guido Dartmann, Gerd Ascheid

  • Study on Reinforcement Learning for Next-generation (6G) wireless communications

    Description: Here at the Chair of Distributed Signal Processing (DSP) we have several master thesis offers to study reinforcement learning (RL) algorithms have shown to perform well under dynamic environments and perform efficiently. However, to cope with the low latency and high-reliability requirements of modern applications, these models must be optimized further. Our objective is to study RL techniques through which the training process can be optimized in order to make them applicable in a rate constrained communication system.
    Supervisor: Dr. H. Kremo

  • Tackling Avalanches in Spiking Neural Network Accelerators

    Description: In this master thesis, a standard spiking neural network is trained using Tensorflow. The avalanches are shown by means of software. Next, the amount and timing of avalanches are modeled mathematically. Furthermore, the software model is attached to a SystemC model of the on-chip network. The performance impact of avalanches is quantified. Finally, an architectural optimization is proposed to overcome performance limitations. 
    Supervisor: Dr.-Ing. Jan Moritz Joseph

More Topics on request

On the following pages some open offers are listed. In addition, there is the possibility for interested students to make an appointment by e-mail.

Tutors: Dominik Šišejković