Master and Bachelor theses offers

Bachelor Theses offers

Master Theses offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Development of novel wireless transmission technologies

    Supervisor: Dr. Haris Kremo via
    Description:: Here at the Chair of Distributed Signal Processing (DSP) we have several master thesis offers to develop novel wireless transmission technologies (in particular physical-layer design) for modulation/demodulation, optimization, signal design, etc.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • Hardware Security: Secure Processor Design

    Supervisor: Lennart Reimann
    Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

  • Machine Learning for Security

    Supervisor: Dominik Šišejković
    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • Neuromorphic Hardware Security

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to investigate novel Hardware Security vulnerabilities and their countermeasure of neuromorphic computing architecture. In particular, the student will have the unique opportunity to work with the real ReRAM crossbars to perform measurements within our labs.

  • Neuromorphic Virtual Platforms

    Supervisor: Felix Staudigl
    Description: This Master/Bachelor Thesis aims to develop a virtual prototype to perform a system exploration concerning parameters like power consumption and performance. The virtual prototype will be implemented in C++ together with SystemC/TLM.

  • NoC design-space exploration for neuromorphic massive multicore systems (copy 1)

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to model NoCs with a fast and abstract performance model. The model shall cover the state of routers in slices of time. Input bandwidth, output bandwidth and network latency must be estimated.

  • Sensing Communications for 6G wireless systems

    Supervisor: Dr. Haris Kremo via
    Description:: At the Chair of Distributed Signal Processing (within the Institute for Communication Technologies and Embedded Systems) we have several offers for master thesis to develop novel technologies related to Sensing Communications in particular related to advancement of physical-layer signal processing and machine learning.

  • SIEM Sensor für virtuelle Kraftwerke

    Tutors: Guido Dartmann, Gerd Ascheid

  • Study on Reinforcement Learning for Next-generation (6G) wireless communications

    Description: Here at the Chair of Distributed Signal Processing (DSP) we have several master thesis offers to study reinforcement learning (RL) algorithms have shown to perform well under dynamic environments and perform efficiently. However, to cope with the low latency and high-reliability requirements of modern applications, these models must be optimized further. Our objective is to study RL techniques through which the training process can be optimized in order to make them applicable in a rate constrained communication system.
    Supervisor: Dr. H. Kremo

  • We are hiring! Programmers (C++, Python), Data Scientists, Hardware Engineers

    Supervisor: Dr. Jan Moritz Joseph
    Description: There is plenty of work in our team. Developing hardware, building prototypes, maintaining open-source software, or inventing new ML models? That’s all possible! We will find a task that fits your profile best.

More Topics on request

On the following pages some open offers are listed. In addition, there is the possibility for interested students to make an appointment by e-mail.

Tutors: Dominik Šišejković