HiWi and WiHi job offers

HiWi / WiHi job offers

  • Abstract TLM-based Model for on-Chip Interconnects

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Using exsiting low-level models for on-chip interconnects, higher-level models can be deduced. Here, we will use our existing ratatoskr open-source simulator on cycle-accurate abstraction level to model the interconnect on a transaction-level model (TLM) accouting for the network topology and the network congestion. Performance and power are to be estimated.

  • Bayesian machine learning on neuromorphic architectures

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Spiking neural networks can perform Bayesian inference in a highly accelerated form. Such models are adaptable and robust with respect to noise. An example is in hearing aids that adapt some of the acquisition parameters in real-time. The goal of this project is to enable Bayesian Machine Learning Algorithm on a neuromorphic compute architecture. The successful candidate will be given a chance to publish his findings (if relevant) to the scientific community through a peer-reviewed publication.

  • Development of an auto-tuner for efficient neural-network mapping for neuromorphic systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: Part of any processor technology is an SDK, whose task it is (amongst others) to map a standard neural-network application, developed with Tensorflow, to a SoC. Therefore, the layers of the neural network must be assigned to cores in the NoC mesh of a  massive-many-core system. The goal of this thesis is to develop an auto-tuner to improve GML’s mapper. The task of the mapper is to assign layers of a neural network to cores in the NoC mesh of a massive-many-core system. The auto-tuner receives a set of optimization parameters, which are considered for optimizing the mapping.

  • Hardware-Security: IP Integrity Protection

    Description: Here at the Chair for Software for Systems on Silicon (SSS), we are looking into novel ways of securing hardware designs (in particular processor cores) against hardware Trojans, taking the complexity of modern circuits into account.
    Supervisor: Dominik Šišejković

  • Hardware Security: Secure Processor Design

    Supervisor: Lennart Reimann
    Description: In this work we would like to address the development and evaluation of tools to elaborate and/or quantify the security properties of a processor design. The properties Confidentiality, Integrity (, Availability) and Authenticity (CI[A]A) need to be protected.

  • High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a the aforementioned framework by a new in-house NoC model. Furthermore, a experiemental setup to assess the NoC's side channels must be implemented (including measurements in the lab).

  • HiWi job offer - Pluto and webportal exercise

    Description: We introduce an interactive learning portal to complement teaching with combination of software and hardware exercises. We defined computer simulation exercises and educational software-defined radio (SDR) platform where baseband functions are implemented in SDR to experience a real-life communication over a wireless channel. The simulations and the hands-on exercises seamlessly merge through reuse of essentially the same C language-based code. The major goals are as follows:
    • Provide interactive web-based platform for the students to remotely, at time of their choice, and with maximum flexibility in execution simulate theoretic concepts covered in class.
    • Provide state-of-the-art hands-on experience to the students with the specified software defined radio. Students can implement, try, and manipulate the code running on the software radio to develop deep understanding of the theoretic concepts learned in class.

    Supervisor: Dr. H. Kremo

  • Machine Learning for Security

    Description: In the context of this work, we will address some selected challenges from the area of hardware security by applying modern machine learning techniques.
    Supervisor: Dominik Šišejković

  • Neuroflow: SW/HW-Interfaces for Neuromorphic Computing

    Supervisor: Felix Staudigl
    Description: In the context of this work, we will invent a novel way of computation in neuromorphic devices. These problems are closely related to existing soltions for Google's TPU-style way of data processing. Their approaches must be translated into the neuromorphic world.

  • NoC design-space exploration for neuromorphic massive multicore systems

    Supervisor: Dr.-Ing. Jan Moritz Joseph
    Description: The goal of this thesis is to extend a SystemC simulator to reflect a next-generation neuromorphic compute architecture. Thereby, the focus is on integrating a cycle-accurate, heavily parametrizable NoC model. This tool shall be subsequently used for NoC-architecture design-space exploration for massively-parallel neuromorphic computer architectures.

  • Pattern Reconstruction from Images for DNA-based Computing

    Description: In this task, you will invent a reconstruction algorithm to identify DNA-inputs using 2D and 3D videos of a micro-fluidic system. The microfluidic system will combine different DNA-snippets and a video is taken of the system. You will develop a reconstruction method (by linear programming, combinatorics of machine learning); the problem can be modeled as a string-matching algorithm.
    Supervisor: Dr.-Ing. Jan Moritz Joseph

  • RISCV plus TensorFlowLite Hardware Platform

    Supervisor: PhD-Ing. Melvin Galicia
    Description: RISCV processors have gained a good level of maturity in the academia and they are trying to breakthrough in the industry. Attaching  RISCV processors to booming commercial technologies like maching learning software is a very promising idea. The job is to bring to life a realization of a platform, where TensorFlow-Lite framework can be compiled and run in an actual RISCV processor.

  • Tackling Avalanches in Spiking Neural Network Accelerators

    Description: In this master thesis, a standard spiking neural network is trained using Tensorflow. The avalanches are shown by means of software. Next, the amount and timing of avalanches are modeled mathematically. Furthermore, the software model is attached to a SystemC model of the on-chip network. The performance impact of avalanches is quantified. Finally, an architectural optimization is proposed to overcome performance limitations. 
    Supervisor: Dr.-Ing. Jan Moritz Joseph

  • Wi-Hi Position: Programming

    Description: The ICE is looking for a Bachelor graduate who will be employed for software development as a half-time scientific assistant (WiHi, 20h per week).
    Tutor: Shawan Mohammed