Designing an ultra-efficient memristor-based Deep Learning Accelerator (DLA)

Here at the Chair for Software for Systems on Silicon (SSS), we investigate the energy efficiency of memristor-based neuromorphic platforms for Deep Learning Acceleration (DLA).

In this project, you will contribute to this research by developing the RTL of a memristor-based DLA engine and deploying a prototype on an FPGA board.

Artificial Neural Networks, in particular Deep Learning, drastically improve the way computers see, hear and interact with their users and environment. However, Deep Learning applications demand high processing and memory throughput resulting in enormous energy usage.

For this reason, the design of energy-efficient HW platforms remains a significant challenge. Neuromorphic computing architectures aim to reduce the energy cost of NN processing by placing memory and compute kernels tightly coupled together, hence reducing the number of costly data movements.

Resistive RAM (ReRAM) is an emerging non-volatile memory technology that offers excellent density, power efficiency and compatibility with the established CMOS design process. These qualities make it an ideal element for implementing novel neuromorphic computing platforms.

• Define a hierarchical/modular HW architecture based on existing assets (instruction set, interfaces, target ReRAM).
• RTL implementation using Verilog / VHDL / high-level synthesis.
• Validation against system-level simulation models.
• Enable tracing of operations and power consumption measurements.
• Integration and test with real memristor cross-bars.

Must have:

• Experience with HW synthesis and FPGA-based design.
• Programming experience with C++/Python.
• Interest in computer architectures and ANNs.
• (Optional) Knowledge in power measurement and test systems.

In case of interest, please send me an email including the following:

• A very brief description of your background and motivation.
• Latest transcript of records.
• CV.