NoC design-space exploration for neuromorphic massive multicore systems

Background

Ultra-low power, fully programmable neuromorphic computing is one of the important research topic in industry and academia. This work is conducted in cooperation with an international silicon company dedicated to neuromorphic computing for sensor analytics and machine learning – powered by brain-inspired technology. Their architecture is constructed as a massively parallel SoC (over 100 cores), optimized for machine-learning inference and data-flow applications.

Description

The goal of this thesis is to extend a SystemC simulator to reflect a next-generation neuromorphic compute architecture. Thereby, the focus is on integrating a cycle-accurate, heavily parametrizable NoC model. This tool shall be subsequently used for NoC-architecture design-space exploration for massively-parallel neuromorphic computer architectures.

Tasks

  • Develop a methodology to optimize NoC architectures for SOTA CNNs such as Resnet or MobileNet (i.e., optimize buffer-depth, routing methodology, virtual channel count, topology, etc.) 
  • Evaluate the impact of the NoC on the overall system performance
  • Identify common NoC traffic patterns in neuromorphic applications

Requirements

Must have:

  • Master student with electrical/computer engineering background
  • Available for a period of 9-12 months
  • Strong background in Computer Architecture or Advanced Digital System Design
  • Strong programming background (preferably with SystemC/C++)
  • Strong background in advanced computer architectures and digital design
  • Good understanding of networks on chips architectures and concepts
  • “Can-do” mentality, excellent problem-solving capabilities, and the motivation to dive deep into a novel neuromorphic compute architecture

Good to have:

  • Understanding of (convolutional) neural networks