NoC design-space exploration for neuromorphic massive multicore systems
Background
Fast and accurate models are an everlasting topic in virutal protoyping. This also holds for performance modeling of on-chip communication networks (NoCs). A wide range of accurate yes slow models exist; faster models are scarse and often inaccurate. This is tackled in this thesis.
Description
The goal of this thesis is to extend a SystemC simulator to model NoCs with a fast and abstract performance model. The model shall cover the state of routers in slices of time. Input bandwidth, output bandwidth and network latency must be estimated.
Tasks
- Develop a methodology to model NoC architectures
- Evaluate the impact of the NoC on the overall system performance
- Include the model into Gem5-full-system simulation
Supervisor
Requirements
Must have:
- Good C++ and Python knowledge
- Interest in computer architectures