2. Teaching
  3. High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

High-performance FPGA-based NoC Co-Emulation-Simulation Framework for HW-Security Evaluation

Background

FPGA emulation allows for very high performance with speedups of 1000x vs. simulations. Furthermore, they enable evaulation of thermal, electromagnetic and power side-channels. In a previous work, we implemented an FPGA-based network (NoC) emulation, see https://ieeexplore.ieee.org/abstract/document/8279775. Here, we will extend this to measure the NoC's security.

Description

The goal of this thesis is to extend a the aforementioned framework by a new in-house NoC model. Furthermore, a experiemental setup to assess the NoC's side channels must be implemented (including measurements in the lab).

Tasks

  • Extension of framework for novel router architecutre
  • Bringing project to non-legacy FPGA board
  • Designing an easy-to-use tool flow
  • Setting up security lab
  • Conducting side-channel analysis

Supervisor

Dr.-Ing. Jan Moritz Joseph

Requirements

Must have:

  • Master student with computer science or electrical/computer engineering background
  • Available for a period of 9-12 months
  • Strong background in HW-design for FPGAs (VHDL or Verilog)
  • Strong programming background (preferably C++)
  • “Can-do” mentality, excellent problem-solving capabilities, and the motivation to dive deep into FPGA architectures and timing tricks

Good to have:

  • Linux Kernel development skills
  • Good understanding of networks on chips architectures and concepts