Seminar: Embedded System Design
Supervisors per topic:
- Hardware Security: Farhad Merchant, Elmira Moussavi
- Neuromorphic Computing for AI Accelerators: Jan Moritz Joseph
Course language: English
More information and registration:
- The registration is done in three steps:
- Register via RWTH online
- Attend the introduction event (see below)
- Apply via email (explained during the event) for a position in the seminar
- A zoom link is automatically provided upon registration via RWTH online. In case of issues, contact one of the supervisors.
- The introduction events:
- Hardware Security: 21.04, 18:00h via zoom.
- Neuromorphic computing: 22.04, 18:00h via zoom.
The embedded system design seminar covers two sets of topics:
- Hardware security
- Neuromorphic computing for AI accelerators
More information is given below.
Hardware security: Nowadays the semiconductor industry relies on designing and fabricating integrated circuits (ICs) in a globalized multi-player environment. This production ecosystem has led to serious concerns such as intellectual property (IP) piracy, IC counterfeiting and reverse engineering. Furthermore, due to potentially untrusted designers and foundries, malicious modifications of ICs known as hardware Trojans have been introduced. These modifications enable a large variety of attacks including Denial of Service (DoS) and information leakage attacks. Under the hardware security research theme, we aim to cover a wide range of topics in the domain of hardware security. We plan to develop new techniques for the next generation secure hardware architectures and secure software stacks.
Neuromorphic computing: Artificial Intelligence (AI) has become an important driver for innovation, as it is a nearly universally applicable method on all of computer science. As AI workloads are compute-demanding tasks, specialized hardware accelerators have gained traction leading to many products such as Google’s tensor processing unit (TPU). Neuromorphic computing is a novel approach using in-memory computing and post-CMOS technologies to improve AI accelerators. The promises are manyfold, e.g., reduced power consumption and improved latency. Hence, a plethora of research works on devices, architectures, systems, and security have been introduced. In this seminar, we cover techniques and architectures presented in the recent literature to build and improve AI accelerators using neuromorphic computing both for cloud and edge applications. We also dwell briefly on device-level limitations and their mitigation techniques from the physical and the system-integration perspective.