Laboratory: Digital IC Design Lab

Lecturer:  Rainer Leupers

Supervisor:  Sebastian Birke

Typ:  Praktikum

Credits: 4

Course language: : English (some remaining german material)

Preliminary discussion and registration: 27.04.2021 18:00 Uhr

Inhalt

In this project, students are taught to design and implement integrated circuits. The students learn the complete process from the initial architecture concept down to the layout level.

Topics:

  • Architectural design and modeling (Register Transfer Level)
  • VHDL implementation of the RTL model
  • Gatelevel Synthesis with Design Compiler
  • Formal verification with formality
  • Simulation with QuestaSim (MentorGraphics/Siemens) and Synopsys VCS (RTL and Gatelevel)
  • Static timing analysis with Synopsys PrimeTime
  • If applicable, Layout with Cadence Encounter (Foundation Flow)
  • Power estimation with Synopsys PrimePower (post synthesis and post layout)
  • Simple handwritten VHDL test bench
  • Extended testbench (from the Kaeslin book, “Digital Integrated Circuit Design”)
  • If applicable, UVM-based test bench (Constrained Random Verification)
  • If applicable, SystemC/C++ reference model
  • If applicable, Manual floor plan
  • Crashkurs VHDL, Git

Course schedule:

  • Implementation of a simple adder (entity, data path, register) including a simple testbench (component, instantiation as well as RTL simulation (QuestaSim) and synthesis
  • Implementation of an accumulator (Mux, State Machine) +Tb +Sim +Synthesis +formal verification
  • Customize extended testbench
  • Post-synthesis power simulation (VCS, PrimeTime, ...)
  • Adjust layout scripts and create and analyze layout
  • Post Layout Power estimation
  • Repeat with larger design

Requirements:

The prerequisite for participation in the project is a Bachelor's degree. Bachelor students are also considered if they have achieved 120 credits. Especially basic knowledge from the lecture "Grundgebiete der Informatik III" is required.

Dates

The event starts in the second week of lectures. The further dates will be discussed with the group at the first appointment. We prefer a kind of "block course", i.e. e.g. a few days full time, or one complete day per week until all tasks have been completed. Afterwards the students get a project task, which they solve independently to consolidate the learned knowledge. The time allocation is then flexible.