MAPS: MPSoC Application Programming Studio (SSS)

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Motivation

Programming embedded Multicore platforms is a grand challenge for SoC providers and users today, posing a multitude of SW design issues: What is the right MPSoC programming model that captures both parallel computations and certified sequential C code? How to parallelize legacy C code? How to meet real-time constraints? How to schedule for multitasking? How to achieve optimal utilization of custom processing elements? How to minimize communication overhead? How to explore the vast SW mapping design space?

Traditional compiler technology does not scale for MPSoC. As a result of a long-term R&D investment, ICE at RWTH Aachen University has developed the MAPS Compiler (MPSoC Application Programming Studio), a tool framework with an Eclipse-based IDE that eases programming of heterogeneous MPSoC architectures, while ensuring optimal system performance. Its input language is CPN, an easy-to-use C extension that models concurrent processes and applications as well as legacy code. Based on novel code analysis and profiling technologies, MAPS performs automated code partitioning as well as optimized spatial and temporal task to processor assignment. The output is partitioned C code that can be compiled by the native C compilers of the MPSoC processing elements. By executing the code on a real or virtual target platform, the user can quickly evaluate the result quality and, if required, explore further SW mapping options.

MAPS features

  • Compilation framework for multi-core systems (heterogeneous or homogeneous) for SW developers
  • C-based extension for parallel programming
  • C-based source-to-source translation to leverage the existing C compiler technology for multi-core processing elements
  • Advanced scheduling and mapping of parallel applications
  • Sequential C partitioning facilities
  • Retargetability of the compiler framework towards different multi-core platforms
  • Collaborative in working with state-of-the-art ESL (Electronic System Level) design tools and other silicon vendor SW tools

MAPS programming model

  • Multiple (potential simultaneous) applications
  • Each given in either sequential C code or C extension (CPN) for Kahn Process Networks (KPNs)
  • Real-time class plus constraints
  • Preferred PE type
  • Concurrency graph models multitasking scenarios
  • Automated code (re)partitioning
  • Mixed static/dynamic task scheduling

MAPS Sequential Flow

The current practice of software development relies on program transformation instead of designing everything from scratch. This is a fact in the context of MPSoC programming, as it involves parallelizing legacy sequential code to distribute the workload among the available cores, in order to achieve performance improvements. This is an extremely error-prone and time consuming task, as the developer might not be familiar with the code and in most of the cases there is not enough documentation available. The MAPS framework addresses this issue by providing a flow, which eases the process of transforming sequential C code into CPN. The sequential flow extracts multiple forms of parallelism such as Task, Data and Pipeline level parallelism. Once the flow has analyzed the input code, parallelization suggestions are presented graphically. This allows an easy interaction with the developer and an intuitive presentation of the results, thus enabling a transparent derivation of the CPN representation.

History / Spin-off

Following the acquisition of the 40 million Euros UMIC Excellence Cluster by RWTH in 2006, ICE began to massively invest R&D resources in novel multicore programming tools, anticipating forthcoming industrial demands. An international user workshop held by ICE in 2011, as well as early project engagements with industry partners reconfirmed the strong need for advanced multicore software tools and focused ICE´s R&D roadmap. The acquisition of significant seed funding from the German EXIST program in 2013 paved the way towards further financial investments and accelerated commercialization process. As a result, Silexica Software Solutions GmbH was founded in Aachen, Germany, in August 2014 as a spin-off from the ICE to productize MAPS technologies. Meanwhile ICE continues ground-breaking research activities on various aspects of multicore programming tools.  

Dörpinghaus, M., Ascheid, G., Meyr, H. and Mathar, R.: Optimal PSK signaling over stationary Rayleigh fading channels, in Proceedings: IEEE ISIT(Toronto, Canada), Jul. 2008


Ispas, A., Schneider, C., Ascheid, G. and Thomä, R.: Analysis of Local Quasi-Stationarity Regions in an Urban Macrocell Scenario, in Proc. 71st IEEE Veh. Tech. Conf. (VTC 2010-Spring)(Taipei, Taiwan), May. 2010, 10.1109/VETECS.2010.5494098 ©2010 IEEE


Gao, L., Huang, J., Ceng, J., Leupers, R., Ascheid, G. and Meyr, H.: TotalProf: A Fast and Accurate Retargetable Source Code Profiler, in International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS 2009)(Grenoble, France), in International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS 2009)(Grenoble, France), 2009


Karuri, K., Leupers, R., Ascheid, G. and Meyr, H.: A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs) for Application Specific Processor Customization through Instruction-Set Extensions (ISEs), pp. pp. 204-214, 2009


Schumacher, C., Leupers, R., Petras, D. and Hoffmann, A.: parSC: Synchronous Parallel SystemC Simulation on Multi-Core Host Architectures, in International Conference on Hardware/Software Codesign and System Synthesis(Scottsdale, USA), Oct. 2010


Ispas, A., Schneider, C., Ascheid, G. and Thomä, R.: On Non-Stationary Urban Macrocell Channels in a Cooperative Downlink Beamforming Scenario, in Proc. 72nd IEEE Veh. Tech. Conf. (VTC 2010-Fall)(Ottawa, Canada), Sep. 2010, 10.1109/VETECF.2010.5594355 ©2010 IEEE


Ramakrishnan, V. and Ascheid, G.: A Feasibility Study of a Component-Based Fully-Software Waveform Implementation for SDR, in International Conference on RF & Signal Processing (Vijayawada, India), Jan. 2010


Castrillon, J., Velasquez, R., Stulova, A., Sheng, W., Ceng, J., Leupers, R., Ascheid, G. and Meyr, H.: Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms, in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '10)(Dresden, Germany), pp. 753--758, Mar. 2010, ISBN: 978-3-98108-016-2


Dartmann, G., Afzal, W., Gong, X. and Ascheid, G.: Joint Optimization of Beamforming, User Scheduling, and Multiple Base Station Assignment in a Multicell Network, in Proceedings of IEEE Wireless Communications and Networking Conference (WCNC), pp. 209 -214, Mar. 2011, ISSN: 1525-3511, 10.1109/WCNC.2011.5779162 ©2011 IEEE


Ispas, A., Bernadó, L., Dörpinghaus, M., Ascheid, G. and Zemen, T.: On the Use of Mismatched Wiener Filtering for the Characterization of Non-Stationary Channels, in Proc. 44th Annu. Asilomar Conf. Signals, Syst., Comput.(Pacific Grove, CA, USA), pp. 1971-1975, Nov. 2010, ISSN: 1058-6393, 10.1109/ACSSC.2010.5757885


Borlenghi, F., Witte, E. M., Ascheid, G., Meyr, H. and Burg, A.: A 772 Mbit/s 8.81 bit/nJ 90 nm CMOS Soft-Input Soft-Output Sphere Decoder, in IEEE Asian Solid-State Circuits Conference (A-SSCC), pp. 297 -300, Nov. 2011, 10.1109/ASSCC.2011.6123571 ©2011 IEEE


Stulova, A., Ceng, J., Sheng, W., Castrillon, J. and Leupers, R.: A Co-simulation Framework for MPSoC Run-Time Behavior Analysis in Early System Design, in Swedish Workshop on Multi-Core Computing, Nov. 2009


Ishaque, A. and Ascheid, G.: On the Efficient Mitigation of Phase Noise in MIMO-OFDM Receivers, in International Symposium on Signals, Systems and Electronics (ISSSE)(Potsdam), pp. 1 - 6 , IEEE, Oct. 2012, ISBN: 978-1-46734-453-1, ISSN: 2161-0819, 10.1109/ISSSE.2012.6374308 ©2012 IEEE


Borlenghi, F., Witte, E. M., Ascheid, G., Meyr, H. and Burg, A.: A 2.78 mm² 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver, in IEEE European Solid-State Circuits Conference (ESSCIRC), Sep. 2012, 10.1109/ESSCIRC.2012.6341257 ©2012 IEEE


Sheng, W., Schürmans, S., Odendahl, M., Leupers, R. and Ascheid, G.: Automatic Calibration of Streaming Applications for Software Mapping Exploration, in Design & Test, IEEE, Vol. 30, No. 3, pp. 49-58 , Mar. 2013, ISSN: 2168-2356, 10.1109/MDT.2012.2204852 ©2013 IEEE


Dartmann, G., Zandi, E. and Ascheid, G.: A Modified Levenberg-Marquardt Method for the Bidirectional Relay Channel, in IEEE Transactions on Vehicular Technology, IEEE, pp. 4096 - 4101 , Oct. 2014, ISSN: 0018-9545, 10.1109/TVT.2014.2306204 ©2014 IEEE


Auras, D., Leupers, R. and Ascheid, G.: A Novel Class of Linear MIMO Detectors With Boosted Communications Performance: Algorithm and VLSI Architecture, in Proceedings of the 2014 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)(Tampa, FL, USA), pp. 41 - 47, IEEE, Jul. 2014, ISBN: 978-1-47993-763-9, 10.1109/ISVLSI.2014.16 ©2014 IEEE


Aguilar, M. A., Eusse, J. F., Ray, P., Leupers, R., Ascheid, G., Sheng, W. and Sharma, P.: Parallelism Extraction in Embedded Software for Android Devices, in Proceedings of the XV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), Jul. 2015, 10.1109/SAMOS.2015.7363654 ©2015 IEEE


Li, H., Wang, H. and Ascheid, G.: Long-Term Window Scheduling for eICIC with User Mobility in LTE HetNets, in Proceedings of IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), pp. 1046 - 1051 , Aug. 2015, 10.1109/PIMRC.2015.7343452 ©2015 IEEE


Rákossy, Z. E., Acosta Aponte, A., Noll, T., Leupers, R., Ascheid, G. and Chattopadhyay, A.: Design and Synthesis of Reconfigurable Control-Flow Structures for CGRA, in International Conference on ReConFigurable Computing and FPGAs (ReConFig),(Cancun, Mexico), Dec. 2015, 10.1109/ReConFig.2015.7393298 ©2015 IEEE


Cepheli, , Lücken, V., Karabulut Kurt, G., Dartmann, G. and Ascheid, G.: Physical Layer Security in the Last Mile Technology of Mobile Networks, in Protecting Mobile Networks and Devices: Challenges and Solutions, Nov. 2016


Leupers, R.: Technology Transfer in Computing Systems: The TETRACOM Approach, in Design Automation & Test in Europe (DATE), Dresden (Germany), pp. 834-837, Mar. 2016, ISBN: 978-3-98153-706-2


Cepheli, , Dartmann, G., Karabulut Kurt, G. and Ascheid, G.: An Encryption Aware Physical Layer Security System, in ICC2017: IEEE International Workshop on Smart Communication Protocols and Algorithms, IEEE, May. 2017, 10.1109/ICCW.2017.7962834 ©2017 IEEE


Aguilar, M. A., Eusse, J. F., Ray, P., Leupers, R., Ascheid, G., Sheng, W. and Sharma, P.: Towards Parallelism Extraction for Heterogeneous Multicore Android Devices, in International Journal of Parallel Programming, Vol. 45, No. 6, Springer, pp. 1592-1624, Dec. 2017, ISSN: 1573-7640, 10.1007/s10766-016-0479-5


Rákossy, Z. E.: Modeling, analysis and exploration of layers : a 3D computing architecture, Ph. D. Dissertation RWTH Aachen University, Dec. 2015


Schürmans, S., Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Chen, X.: Frequency-Aware ESL Power Estimation for ARM Cortex-A9 Using a Black Box Processor Model, in (ACM TECS), Vol. 16, No. 1, ACM, pp. 26:1--26:26, Oct. 2016, ISSN: 1539-9087, 10.1145/2987375