MAPS: MPSoC Application Programming Studio (SSS)
Programming embedded Multicore platforms is a grand challenge for SoC providers and users today, posing a multitude of SW design issues: What is the right MPSoC programming model that captures both parallel computations and certified sequential C code? How to parallelize legacy C code? How to meet real-time constraints? How to schedule for multitasking? How to achieve optimal utilization of custom processing elements? How to minimize communication overhead? How to explore the vast SW mapping design space?
Traditional compiler technology does not scale for MPSoC. As a result of a long-term R&D investment, ICE at RWTH Aachen University has developed the MAPS Compiler (MPSoC Application Programming Studio), a tool framework with an Eclipse-based IDE that eases programming of heterogeneous MPSoC architectures, while ensuring optimal system performance. Its input language is CPN, an easy-to-use C extension that models concurrent processes and applications as well as legacy code. Based on novel code analysis and profiling technologies, MAPS performs automated code partitioning as well as optimized spatial and temporal task to processor assignment. The output is partitioned C code that can be compiled by the native C compilers of the MPSoC processing elements. By executing the code on a real or virtual target platform, the user can quickly evaluate the result quality and, if required, explore further SW mapping options.
- Compilation framework for multi-core systems (heterogeneous or homogeneous) for SW developers
- C-based extension for parallel programming
- C-based source-to-source translation to leverage the existing C compiler technology for multi-core processing elements
- Advanced scheduling and mapping of parallel applications
- Sequential C partitioning facilities
- Retargetability of the compiler framework towards different multi-core platforms
- Collaborative in working with state-of-the-art ESL (Electronic System Level) design tools and other silicon vendor SW tools
MAPS programming model
- Multiple (potential simultaneous) applications
- Each given in either sequential C code or C extension (CPN) for Kahn Process Networks (KPNs)
- Real-time class plus constraints
- Preferred PE type
- Concurrency graph models multitasking scenarios
- Automated code (re)partitioning
- Mixed static/dynamic task scheduling
MAPS Sequential Flow
The current practice of software development relies on program transformation instead of designing everything from scratch. This is a fact in the context of MPSoC programming, as it involves parallelizing legacy sequential code to distribute the workload among the available cores, in order to achieve performance improvements. This is an extremely error-prone and time consuming task, as the developer might not be familiar with the code and in most of the cases there is not enough documentation available. The MAPS framework addresses this issue by providing a flow, which eases the process of transforming sequential C code into CPN. The sequential flow extracts multiple forms of parallelism such as Task, Data and Pipeline level parallelism. Once the flow has analyzed the input code, parallelization suggestions are presented graphically. This allows an easy interaction with the developer and an intuitive presentation of the results, thus enabling a transparent derivation of the CPN representation.
History / Spin-off
Following the acquisition of the 40 million Euros UMIC Excellence Cluster by RWTH in 2006, ICE began to massively invest R&D resources in novel multicore programming tools, anticipating forthcoming industrial demands. An international user workshop held by ICE in 2011, as well as early project engagements with industry partners reconfirmed the strong need for advanced multicore software tools and focused ICE´s R&D roadmap. The acquisition of significant seed funding from the German EXIST program in 2013 paved the way towards further financial investments and accelerated commercialization process. As a result, Silexica Software Solutions GmbH was founded in Aachen, Germany, in August 2014 as a spin-off from the ICE to productize MAPS technologies. Meanwhile ICE continues ground-breaking research activities on various aspects of multicore programming tools.
- Ceng, J., Castrillon, J., Sheng, W., Scharwächter, H., Leupers, R., Ascheid, G., Meyr, H., Isshiki, T., and Kunieda, H.:MAPS: An Integrated Framework for MPSoC Application Parallelization,
in 45th Design Automation Conference (DAC '08) (Anaheim, CA, USA), pp. 754–759, ACM, June 2008, ISBN: 978-1-60558-115-6.
- Task Management in MPSoCs: an ASIP Approach,
in Proceedings of the 2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD '09) (San Jose, California, USA), pp. 587–594, Nov. 2009, ISBN: 978-1-60558-800-1.
- A High-Level Virtual Platform for Early MPSoC Software Development,
in International Conference on Hardware/Software Codesign and System Synthesis (CODES-ISSS 2009) (Grenoble, France), pp. 11–20, Oct. 2009, ISBN: 978-1-60558-628-1.
- Leupers, R., Vajda, A., Bekooij, M., Ha, S., Doemer, R., and Nohl, A.:Programming MPSoC platforms: Road works ahead!,
in Proc. of the Design, Automation and Test in Europe Conference and Exhibition (DATE 2009) (Nice, France), pp. pp. 1584–1589, 2009.
- Ramakrishnan, V., Adrat, M., Kempf, T., Castrillon, J., Ascheid, G., Leupers, R., Meyr, H., and Antweiler, M.:SDR Waveform Development: Towards Tool Assisted Mapping and Evaluation in the Nucleus Concept,
in Proceedings of the SDR'09 Technical Conference and Product Exposition (Washington D.C., USA), pp. 1–18, Dec. 2009.
- Castrillon, J., Schürmans, S., Stulova, A., Sheng, W., Kempf, T., Ishaque, A., Leupers, R., Ascheid, G., and Meyr, H.:Component-based Waveform Development: the Nucleus Tool Flow for Efficient and Portable SDR,
in Proceedings of the SDR'10 Technical Conference and Product Exposition (Washington D.C., USA), pp. 476–481, Dec. 2010.
- Castrillon, J., Velasquez, R., Stulova, A., Sheng, W., Ceng, J., Leupers, R., Ascheid, G., and Meyr, H.:Trace-based KPN Composability Analysis for Mapping Simultaneous Applications to MPSoC Platforms,
in Proceedings of the Conference on Design, Automation and Test in Europe (DATE '10) (Dresden, Germany), pp. 753–758, Mar. 2010, ISBN: 978-3-98108-016-2.
- MPSoC Programming using the MAPS Compiler,
in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC '10) (Taipei, Taiwan), pp. 897–902, Jan. 2010, ISBN: 978-1-42445-766-3.
- Software Compilation Techniques for MPSoCs ,
no. 10.1007/978-1-4419-6345-1_23 in Handbook of Signal Processing Systems, Heidelberg: Springer, 2010, ch. 23, pp. 639–678.
- Leupers, R., Thiele, L., Nie, X., Kienhuis, B., Weiss, M., and Isshiki, T.:Cool MPSoC Programming,
in Proc. of the Design, Automation and Test in Europe Conference (DATE 2010) ( Dresden, Germany), pp. 1488–1493, EDAA, Mar. 2010, ISBN: 978-3-98108-016-2.
- Automatic Calibration of Streaming Applications for Software Mapping Exploration,
in Proceedings of the International Symposium on System-on-Chip (SoC) pp. 136–142, Nov. 2011, 10.1109/ISSOC.2011.6089217, ©2011 IEEE.
- Throughput Driven Transformations of Synchronous Data Flows for Mapping to Heterogeneous MPSoCs,
in SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation July 2012, ISBN: 978-1-46732-296-6, ©2012 IEEE.
- Automated Code Generation of Streaming Applications for C6000 Multicore DSPs,
in 5th European DSP Education and Research Conference Sept. 2012, ©2012 IEEE.
- FIFO Exploration in Mapping Streaming Applications onto the TI OMAP3530 Platform: Case Study and Optimizations,
in IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12) Sept. 2012, ©2012 IEEE.
- A Compiler Infrastructure for Embedded Heterogeneous MPSoCs ,
in 2013 International Workshop on Programming Models and Applications for Multicores and Manycores (PMAM 2013) (New York, NY, USA), pp. 1–10, ACM, Feb. 2013, ISBN: 978-1-45031-908-9, 10.1145/2442992.2442993.
- Automatic Calibration of Streaming Applications for Software Mapping Exploration,
Design & Test, IEEE, vol. 30, pp. 49–58 , Mar. 2013, 10.1109/MDT.2012.2204852, ©2013 IEEE.
- Split-Cost Communication Model for Improved MPSoC Application Mapping,
in Proceedings of the International Symposium on System-on-Chip (SoC) Oct. 2013, 10.1109/ISSoC.2013.6675280, ©2013 IEEE.
- Improving Performance and Productivity for Software Development on TI Multicore DSP Platforms,
in Proceedings of the 6th European Embedded Design in Education and Research Conference (EDERC) pp. 31–35, Sept. 2014, 10.1109/EDERC.2014.6924353, ©2014 IEEE.
– Best Presentation Award –.
- A Toolflow for Parallelization of Embedded Software in Multicore DSP Platforms,
in Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems (SCOPES) (New York, NY, USA), pp. 76–79, ACM, June 2015, ISBN: 978-1-45033-593-5, 10.1145/2764967.2771936.
- Parallelism Extraction in Embedded Software for Android Devices,
in Proceedings of the XV International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS) July 2015, 10.1109/SAMOS.2015.7363654, ©2015 IEEE.
- Extraction of Kahn Process Networks from While Loops in Embedded Software,
in 12th IEEE International Conference on Embedded Software and Systems (ICESS) pp. 1078–1085, Aug. 2015, 10.1109/HPCC-CSS-ICESS.2015.158, ©2015 IEEE.
- Unified Identification of Multiple Forms of Parallelism in Embedded Applications,
ACM SRC at 24th International Conference on Parallel Architectures and Compilation Techniques (PACT), Oct. 2015.
– Gold Medal @ ACM Student Research Competition (SRC) –.
- Automatic Parallelization and Accelerator Offloading for Embedded Applications on Heterogeneous MPSoCs,
in 53rd Design Automation Conference (DAC) (Austin, TX, USA), June 2016, ISBN: 978-1-45034-236-0, 10.1145/2897937.2897991.
– HiPEAC Paper Award –.
- Power-Aware Multicore Software Development,
Embedded World Conference 2016, Feb. 2016.
- Towards Effective Parallelization and Accelerator Offloading for Heterogeneous Multicore Embedded Systems,
in Proceedings of the Twelfth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES) HiPEAC, July 2016.
– Abstract –.
- Schedule-Aware Loop Parallelization for Embedded MPSoCs by Exploiting Parallel Slack,
in 20th Design Automation and Test in Europe Conference (DATE) (Lausanne, Switzerland), pp. 1237–1240 , European Design and Automation Association, Mar. 2017, 10.23919/DATE.2017.7927178, ©2017 IEEE.
- Towards Parallelism Extraction for Heterogeneous Multicore Android Devices,
International Journal of Parallel Programming, vol. 45, pp. 1592–1624, Dec. 2017, 10.1007/s10766-016-0479-5.
- MAPS: A Software Development Environment for Embedded Multicore Applications,
Dordrecht: Springer Netherlands, Sept. 2017.
– doi: 10.1007/978-94-017-7358-4_2-1 –.
Contact: Miguel Aguilar, Diego Pala, Gereon Onnebrink, Milan Copic
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ASIP University Day 2018 took place at ICE on Wednesday, September 26th, 2018
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