DSPstone

DSP Compiler and Processor Evaluation

Projects of the Group on DSP Tools


DSP Compiler and Processor Evaluation - DSPstone



How good are Compilers for DSP-architectures ?

This was the question in 1995 when we started to measure the performance of commercial available DSP-compilers. The performance was measured in such a way that the code produced by the compiler was compared to hand-written assembly code.
Basics of DSPstone

The difference between theses two implementations is measured in terms of code-size and execution time. This was done for several architectures in order to gain information about the abilities of the compilers to address certain features of the architecture.

results of DSPstone

Having a look at the Analog Devices DSP we clearly see that the handwritten assembly code almost outperforms the code produced by the compiler. The execution of the compiler generated code takes 8 times longer than the one written by hand. The code size also is significantly larger. This means if you develop your application with such a compiler you'll have to take a much faster DSP, spend more money for external memory. As a result nearly all time-critical applications are implemented by hand. Some of the reasons why DSP-Compilers are so bad are:

  • unability to use machine idioms (MAC-operation)
  • unability to make use of certain architectural features (zero overhead loops)
  • unability to make use of possible instruction level parallelism

Most of the DSP-compilers are based on GPP-(general purpose-processor) compilers. Therefore the results are not very surprising.


Download the official DSP-Stone sources and the DSP-Stone report here. Updated sources and an updated report for the TI TMS320C54x are available, too.


Publications


News >> News >> News

ICE excursion to the University of Kaiserslautern

During May 24/25, 2018 the ICE team visited the University of Kaiserslautern and met the local

ICE spin-off Silexica raises $18m in Series B funding

Investment will fund the further development of a Simulation Platform for software developers in

Best Paper Award at RAPIDO’18

The Paper titled "ESL Black Box Power Estimation: Automatic Calibration for IEEE UPF 3.0 Power

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