Design for Simulation


Simulating entire systems, such as SoCs, has been an integral part of the system design cycle for many years. Having a simulator available in early stages of the system design enables design space exploration,  HW/SW co-design, early software development and decreases the Time-to-Market, engineering cost and effort. However, modern embedded systems include complex multi-core processors, multi-level memory hierarchies and specialized hardware, such as e.g. machine learning or signal processing accelerators. This complexity leads to a decrease in simulation performance, because every component of the system has to be modeled in the simulator, to achieve sufficient simulation accuracy.

In addition to the rise in hardware complexity enabled by Moore’s law over the past decades, software complexity has increased as well. Modern embedded systems employ a multitude of different applications written in high-level languages such as JavaScript, Java or Python to efficiently utilize the underlying hardware. Moreover, even in embedded systems these applications are often executed inside virtual machines running on top of a hypervisor adding yet another layer of complexity. This sums up to millions of lines of code, potentially containing dangerous bugs that can impact the reliability, safety and security of the embedded systems and every other system that is connected to it. Therefore, fast system simulators are needed to verify the correct and safe operation of all system components.

One way of dealing with the decrease in simulation performance is raising the abstraction level. A typical example of this is so called Transaction Level Modeling (TLM), where communication between components is abstracted by passing messages (transactions) using interface method calls instead of modeling individual signals. Since the ratification of the IEEE 1666-2011 SystemC standard, SystemC TLM2.0, has become the de facto standard for building these system level simulations, which are commonly referred to as Virtual Platforms (VPs).

Project Goals

Nowadays, simply using TLM is not enough to compensate for the enormous rise in system complexity  and novel acceleration technologies, such as fast instruction set simulation, parallel SystemC, host execution or hardware acceleration are required to achieve satisfactory results. It is one of the goals of this project to push research in this domain forward.

In addition, it is important to consider the “simulateability” of the system during system design, because a system simulation will be required as previously explained.
Often constructs that pose no significant limitation on physical hardware, can have a detrimental effect on simulation performance and should therefor be avoided. Therefore, it is a goal of this project to define hardware and software architectures that can be efficiently simulated and to catalog common pitfalls.



Jünger, L., Weinstock, J. H., Leupers, R. and Ascheid, G.: Fast SystemC Processor Models with Unicorn, in Proceedings of the 2019 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Jan. 2019, 10.1145/3300189.3300191