SPAM

A joint DSP compiler project of Synopsys, Princeton University, Aachen University and the MIT

    Project Intention of SPAM

    SPAM is a joint research project on compiler design including the following partners:

    • Synopsys Inc., Mountain View, CA
    • Princeton University, Princeton, NJ
    • Aachen University of Technology, Aachen, Germany
    • Massachusetts Institute of Technology, Cambridge, MA


    The project's intention is to develop a retargetable optimizing compiler for embedded processors .

    For more detailed information refer to the SPAM homepage.

    Role of RWTH Aachen

    Research at RWTH Aachen related to the SPAM project covers the field of

    • compiler benchmarking
    • DSP-oriented language extensions to ANSI-C
    • tool support for fixed-point programming
    • compiled simulation
    • optimized code generation for DSP`s


    The following members of RWTH Aachen are involved in the SPAM project:

    • H. Meyr (head of department),
    • A. Ropers,
    • S. Pees,
    • H. Keding

    Publications

    Zivojnovic, V., Pees, S., Schläger, C., Willems, M., Schoenen, R. and Meyr, H.: DSP Processor/Compiler Co-Design: A Quantitative Approach, in Proc. of the IEEE Symposium on System Synthesis - La Jolla, Nov. 1996


    Post, G., Müller, A. and Meyr, H.: High-level Validation Strategies for Broadband Network Components: A Case Study on Charging Algorithm Design, in IEEE High-Level Design Validation and Test Workshop(Oakland, CA), in IEEE High-Level Design Validation and Test Workshop(Oakland, CA), Nov. 1996


    ten Hagen, K. and Meyr, H.: Top-Down Design mit VHDL: Ein Erfahrungsbericht, in GME Fachtagung Mikroelektronik, in GME Fachtagung Mikroelektronik, pp. 121-126, 1993


    Zepter, P.: Kopplung eines VHDL Simulators an einen Simulator für Signalverarbeitungsalgorithmen, in GME Fachberichte 11 Mikroelektronik, p. 5, 1993


    Zivojnovic, V.: Compilers for digital signal processors, in DSP and Multimedia Technology, Vol. 4, No. 5, pp. 27-45, Aug. 1995


    Ropers, A., Pees, S. and Brueggen, T.: Techniques for compiled Hardware Software Cosimulation, in DSP Germany(Munich), pp. 162-171, Oct. 1998


    Chen, X., Minwegen, A., Hassan, Y., Kammler, D., Li, S., Kempf, T., Chattopadhyay, A. and Ascheid, G.: FLEXDET: Flexible, Efficient Multi-Mode MIMO Detection using reconfigurable ASIP, in The 20th Annual IEEE International Symposium on Field-Programmable Custom Computing Machines, pp. 69-76, Apr. 2012, ISBN: 978-0-76954-699-5, 10.1109/FCCM.2012.22 ©2012 IEEE


    Horstmannshoff, J., Grötker, T. and Meyr, H.: Mapping Multirate Dataflow to Complex RT Level Hardware Models, in ASAP, in ASAP, IEEE, 1997


    Horstmannshoff, J., Grötker, T., Meyr, H., Wloka, M. and Djigande, K.: DSP System Synthesis: Integration of Reusable Building Blocks, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(San Diego), in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT)(San Diego), pp. 774-778, Sep. 1997


    Zivojnovic, V., Pees, S. and Meyr, H.: LISA -- machine description language and generic machine model for HW/SW co-design, in Proceedings of the IEEE Workshop on VLSI Signal Processing(San Francisco), Oct. 1996


    Liao, S., Devadas, S., Keutzer, K., Tjiang, S., Wang, A., Araujo, G., Sudarsanam, A., Malik, S., Zivojnovic, V. and Meyr, H.: Code generation and optimization for embedded digital signal processors, in Hardware Software Codesign, in Hardware Software Codesign, NATO Advanced Study Institute, 1995


    Pees, S., Vaupel, M., Zivojnovic, V. and Meyr, H.: On Core and More: A Design Perspective for Systems-on-a-Chip, in Proceedings of the IEEE International Conference on Application Specific Systems, Architectures, and Processors (ASAP), 1997