MPSoC Exploration

To cope with the ever increasing demands for future applications, system architects have answered this challenge with increasingly parallel architectures, named Multi-Processor Systems on Chip (MPSoCs). As the name implies these platforms incorporate several programmable devices, like General Purpose Processors (GPPs), Digital Signal Processors (DSPs) and/or Application Specific Instruction Set Processors (ASIPs). A communication infrastructure integrated on the same chip enables those processing elements to exchange data among each other. Due to the arising complexity of such systems, software and hardware designers as well as system architects are facing completely new challenges. In our project we focus on the following key issues of MPSoC development:

  • Early software and hardware exploration to determine the performance characteristics of entire MPSoC platforms at a high abstraction level.
  • New programming environments and programming flows supporting software development for MPSoCs.


Motivation and Design Flow

The traditional design flow is subdivided into two decoupled phases. First the functionality of the system is defined during the algorithms exploration phase. Usually this is performed either with an application specific tool including a support library (e.g. SPW and SystemStudio for wireless communications) or by selecting an standard algorithm available (e.g. an H.264 video decoder for a multimedia system). A specification is then created based on the the selected algorithm. This specification serves as the basis for determining the different IP blocks for the processing elements and the communication architecture and finally for the implementation of the the MPSoC prototype. This traditional approach is no longer feasible for the design of large heterogeneous systems, because quantitative architectural considerations are not taken into account prior to the implementation phase.

Due to the high level of detail of the implementation model, its creation is a time-consuming task. As the actual feasibility of the chosen design can only be evaluated once the model has been created, it cannot be determined quickly if further design improvements are necessary and what aspects of the design have to be improved. Additionally, the fine-grained implementation details make it hard to consider global system architecture tradeoffs and lead to applying only local local optimizations.

Therefore we propose a new design flow with and additional intermediate phase. First a high-level MPSoC exploration model is developed, which is used to determine the necessary IP blocks of the MPSoC. Later on the prototype is implemented in an gradual refinement of the abstract exploration model.


This enables an iterative design flow starting with the development of the application. Directly at the beginning, early design space exploration is feasible and developers can evaluate different hardware and software design options based on an abstract simulation model. Our MPSoC programming flow enables a gradual refinement at a later phase of the design. Once the detailed simulation model is available, fine-grained investigation of the MPSoC is possible and verification can be performed If the requirements are not fulfilled developers can modify the application or even go back to the early design space exploration to reevaluate their design decisions including the new experiences and numbers obtained from the detailed model. If the requirements are fulfilled one possible MPSoC implementation has been identified.


Methodologies for Early Design Space Exploration

The key element in our early design space exploration is the Virtual Processing Unit (VPU). In principle the VPU is a generic high-level processor model allowing evaluation of the different software implementations directly at the beginning of the design cycle. It enables the system architect to investigate the mapping of the application tasks with respect to space and time. Spatial mapping denotes the assignment of a task to one of the physical processing elements in the MPSoC platform. Temporal mapping refers to the allocation of a time budget (derived from the number of processing cycles) on this particular processing element. The figure below depicts the main principle.



 Torsten Kempf, Stefan Schürmans


Hadaschik, N., Dörpinghaus, M., Senst, A., Harmjanz, O., Käufer, U., Ascheid, G. and Meyr, H.: Improving MIMO Phase Noise Estimation by Exploiting Spatial Correlations, in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2005)(Philadelphia, PA, USA), in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2005)(Philadelphia, PA, USA), Mar. 2005

Meyr, H., Schliebusch, O., Wieferink, A., Kammler, D., Witte, E. M., Lüthje, O., Hohenauer, M., Braun, G. and Chattopadhyay, A.: Designing and Modeling MPSoC Processors and Communication Architectures, in Building ASIPs: The Mescal Methodology, Springer, pp. 229-280, Jun. 2005, ISBN: 0-387-26057-9

The VPU Technology is integrated into Synopsys Platform Architect (formerly CoWare) and can easily be used in SystemC platforms to quickly model computation blocks on an abstact level. It has been used for example in the following projects:

  • René van den Berg, Walter Tibboel, Rob Wieringa, and Martin Klompstra (NXP Semiconductors). Using the application modeling and mapping methodology for system-level performance analysis. In EE Times online 9/26/2010.
  • T. Kempf, S. Wallentowitz, G. Ascheid, R. Leupers, and H. Meyr (RWTH Aachen University, DE). A Workbench for Analytical and Simulation based Design Space Exploration of Software Defined Radios. In VLSI Design Conference 2009, New Delhi, India, Jan 2009.
  • Schürmans, S., Weingärtner, E., Kempf, T., Ascheid, G., Wehrle, K. and R. Leupers. Towards Network Centric Development of Embedded Systems. In IEEE International Conference on Communications (ICC 2010), Cape Town, South Africa, May 2010.


MPSoC Programming Flow

Programming MPSoC platforms is one of the main issues when trying to exploit the capabilities of the parallel computational resources in an MPSoC. We propose a programming model based on application task graphs, the sequential C programming language along with a tool-aided task mapping process. As illustrated in the figure below, developers can specify the application-to-architecture mapping in a graphical editor. This allows easy evaluation and exploration of different design decisions at an abstract level in an early stage of the design.


The initial goal of the project is to support developers to explore and evaluate their design decisions whether software or hardware ones.