GRACE++ (NoC)

Design Methodology for Network-on-Chip centric Multi-Processor Platforms (MP-SoC)

Welcome to the web-pages of our SystemC based simulation environment for Network-on-Chip (NoC) centric MP-SoC platform exploration. 

Driven by the ever increasing complexity of integrated circuits, we have developed a system level design and refinement methodology based on the SystemC class library. We address design space exploration and performance profiling at the highest possible level of abstraction. System level design starts with the initial functional specification and validation of the system behavior in SystemC. The refinement methodology covers architecture exploration and results in an executable System Architecture Model, which is able to generate the relevant profiling data and to verify if the chosen architecture meets the performance requirements. Comfortable observation and debugging capabilities of large SystemC models are provided by our graphical frontend, which displays inter process communication versus time according to the Message-Sequence-Chart notation.

The complexity and heterogeneity of current and future MP-SoC platforms require diversified on-chip communication schemes (the so-called Network on Chip design paradigm (NoC)) beyond the currently omnipresent shared bus architectures, which is inherently non-scalable. For fast iteration over the immense design space we provide a modular simulation tool that can be easily parametrized to simulate different communication topologies with the behavior of different communication technologies like e.g. AMBA, STBus or Aethereal. During the exploration cycle the framework monitors critical performance parameters and provides the designer with aggregated histogram and graph visualizations of the system bottlenecks. This enables the designer to map the inter-module traffic to an efficient communication architecture.

As joint consideration of communication and computation architecture is indispensable in future SoC designs, the system architect has to navigate through the design space spread by these parts of the system. Therefore our simulation framework also covers the spatial and temporal mapping of the functional application tasks to different processing elements. This mapping enables exploration of dedicated hardware, single threaded processors, as well as shared processing elements with Software- or Hardware Operating Systems.

To enable a seamless path from the system level domain towards the hardware and software implementation domain, the GRACE++ environment serves as an executable specification. HDL and software simulators executing the implementation models are plugged into the system level simulation via our generic co-simulation interface.

Contact

Torsten Kempf, Stefan Wallentowitz, Jens Reinecke, Andreas Wieferink, Tim Kogel, Andrea Kroll (Müllers), Guido Post, Malte Dörper, Christian Huben, Roland Nennen, Olaf Zerres

System Level Design Environment for
Network-on-Chip (NoC) and
Multi-Processor platform (MP-SoC) exploration

Publications

Wieferink, A., Kogel, T., Hoffmann, A., Zerres, O. and Nohl, A.: SoC Integration of Programmable Cores, in International Workshop on IP-Based SoC Design(Grenoble, France), Nov. 2003


Hadaschik, N., Dörpinghaus, M., Senst, A., Harmjanz, O., Käufer, U., Ascheid, G. and Meyr, H.: Improving MIMO Phase Noise Estimation by Exploiting Spatial Correlations, in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2005)(Philadelphia, PA, USA), in IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP 2005)(Philadelphia, PA, USA), Mar. 2005


Schmidt-Knorreck, C., Pacalet, R., Minwegen, A., Deidersen, U., Kempf, T., Knopp, R. and Ascheid, G.: Flexible Front-End Processing for Software Defined Radio Applications using Application Specific Instruction-Set Processors, in Conference on Design and Architectures for Signal and Image Processing, Oct. 2012, ISBN: 978-1-46732-089-4 ©2012 IEEE


Schmitt, L., Grundler, T., Schreyoegg, C., Ascheid, G. and Meyr, H.: Performance of Initial Synchronization Schemes for W-CDMA Systems with Spatio-Temporal Correlations, in IEEE International Conference on Communications (ICC)(Paris, France), in IEEE International Conference on Communications (ICC)(Paris, France), Jun. 2004


Scharwächter, H., Kammler, D., Wieferink, A., Hohenauer, M., Karuri, K., Zeng, J., Leupers, R., Ascheid, G. and Meyr, H.: ASIP Architecture Exploration for Efficient IPSec Encryption: A Case Study, in Software and Compilers for Embedded Systems(Amsterdam, Netherlands), pp. 33--46, Springer Berlin/Heidelberg, Sep. 2004


Leupers, R.: Register Allocation for Common Subexpressions in DSP Data Paths, in Asia South Pacific Design Automation Conference (ASP-DAC)(Yokohama (Japan)), in Asia South Pacific Design Automation Conference (ASP-DAC)(Yokohama (Japan)), Jan. 2000


Ariyamparambath, M., Bussaglia, D., Reinkemeier, B., Kogel, T. and Kempf, T.: A Highly Efficient Modeling Style for Heterogeneous Bus Architectures, in International Symposium on System-on-Chip(Tampere (Finland)), Nov. 2003


Schulz-Rittich, P., Senst, A., Bilke, T. and Meyr, H.: The Effect of Imperfect SNR Knowledge on Multiantenna Multiuser Systems with Channel Aware Scheduling, in IEEE Global Communications Conference (GLOBECOM)(San Francisco, CA, USA), Dec. 2003


Kogel, T., Wieferink, A., Leupers, R., Ascheid, G., Meyr, H., Bussaglia, D. and Ariyamparambath, M.: Virtual Architecture Mapping: A SystemC based Methodology for Architectural Exploration of System-on-Chip Designs, in Int.Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)(Samos (Greece)), Jul. 2003