DSP Compiler and Processor Evaluation - DSPstone
How good are Compilers for DSP-architectures ?
This was the question in 1995 when we started to measure the performance of commercial available DSP-compilers. The performance was measured in such a way that the code produced by the compiler was compared to hand-written assembly code.
The difference between theses two implementations is measured in terms of code-size and execution time. This was done for several architectures in order to gain information about the abilities of the compilers to address certain features of the architecture.
Having a look at the Analog Devices DSP we clearly see that the handwritten assembly code almost outperforms the code produced by the compiler. The execution of the compiler generated code takes 8 times longer than the one written by hand. The code size also is significantly larger. This means if you develop your application with such a compiler you'll have to take a much faster DSP, spend more money for external memory. As a result nearly all time-critical applications are implemented by hand. Some of the reasons why DSP-Compilers are so bad are:
- unability to use machine idioms (MAC-operation)
- unability to make use of certain architectural features (zero overhead loops)
- unability to make use of possible instruction level parallelism
Most of the DSP-compilers are based on GPP-(general purpose-processor) compilers. Therefore the results are not very surprising.
Projects of the Group on DSP Tools
Post, G., Müller, A. and Meyr, H.: High-level Validation Strategies for Broadband Network Components: A Case Study on Charging Algorithm Design, in IEEE High-Level Design Validation and Test Workshop(Oakland, CA), in IEEE High-Level Design Validation and Test Workshop(Oakland, CA), Nov. 1996
Zivojnovic, V.: Compilers for digital signal processors, in DSP and Multimedia Technology, Vol. 4, No. 5, pp. 27-45, Aug. 1995
Liao, S., Devadas, S., Keutzer, K., Tjiang, S., Wang, A., Araujo, G., Sudarsanam, A., Malik, S., Zivojnovic, V. and Meyr, H.: Code generation and optimization for embedded digital signal processors, in Hardware Software Codesign, in Hardware Software Codesign, NATO Advanced Study Institute, 1995
Ropers, A., Pees, S. and Brueggen, T.: Techniques for compiled Hardware Software Cosimulation, in DSP Germany(Munich), pp. 162-171, Oct. 1998
Pees, S., Vaupel, M., Zivojnovic, V. and Meyr, H.: On Core and More: A Design Perspective for Systems-on-a-Chip, in Proceedings of the IEEE International Conference on Application Specific Systems, Architectures, and Processors (ASAP), 1997