Design Flow and Co-Verification
CASTANET: Design Flow and Co-Verification
In order to design efficient systems, the algorithms and their implementations have to be optimized within an interactive and iterative design process. Figure 1 illustrates the environment for high-level design verification. The network simulator OPNET from Mil3 has been designed to provide a comprehensive development environment supporting object-oriented modeling and performance evaluation of communication networks and distributed systems. The design is carried out by building simulation models at different hierachical levels (called network-, node and process domains). The network domain specifies the topology of a networking architecture in terms of high-level devices (called nodes) such as switches and traffic sources, and communication links between them. Within the node domain each node's capability is described in terms of processing, queueing and communication interfaces. The process domain specifies the behavior of processing nodes as communicating extended FSMs. System behavior and performance can be analyzed by means of discrete event simulations.
VHDL is used for the hardware design at the behavioral and RT-level. Validation of VHDL models is performed using Synopsys' VSS. In order to preserve consistency between the more abstract model and the HDL-based implementation we have developed CASTANET, a Configurable ATM Simulation Testbench Applying Network Simulations. CASTANET establishes a coupling between OPNET and the VHDL System Simulator (VSS) for co-verification.