CASTANET: Functional VHDL verification
Figure 2 shows the concept and realisation of the OPNET-VSS simulator coupling. The coupling will be done by a special OPNET interface model that steers a VHDL simulation with test-patterns from the network simulation. The OPNET interface process manages the proper initialization of the VHDL System Simulator (VSS) and handles the message exchange via standard UNIX interprocess communication. In the VSS simulation a CLI-based interface module is instantiated, that receives messages from OPNET interface process. The interface module then performs signal conditioning, e.g. mapping a data structure to bit or word-level signal streams and generation of additional control signals. The response from the VHDL entity under test (EUT) are sent to the OPNET interface node and compared to the model's responses at the system level.
The simultaneous execution of OPNET and VSS is a special case of parallel distributed discrete-event (DE) simulation. A difficult problem in distributed DE simulations is the avoidance of deadlock. DE simulators manages their events via an event list that represents the event distribution over time and maintains a proper time-ordering. Events may be generated for any future time, or the current time but never for past times. Because both simulators are event-driven and therefore both have a notion of time, one has to ensure that neither of them produce events in the past of the other simulator's time basis. Therefore, communication between both simulators is based on the exchange of time-stamped messages. For each message type the CLI interface module maintains a time-stamped message queue containing at least one message that is used to determine timing windows for that VSS is allowed to advance its simulation time. The VSS interface process is also in charge for zero message insertion within these timing windows. Applying this strategy the simulated time of VSS always lags behind OPNET's simulated time. The use of a specific conservative synchronization protocol tha is based on timing windows resolves the possibility of deadlock.
Another important point which has to be considered for the co-simulation of system level network simulators and implementation level HW simulators is the different granularity of time scales. Time units in network simulation can be derived from cell time, whereas the time unit in HW systems is fixed by the HW clock steering bit-level operations. Considering Asynchronous Transfer Mode (ATM) as an example application, one can identify time-periods where idle cells are inserted into the ATM cell (one cell comprises 53 octets) stream. This means that there is a ratio of 1:100 for a simulation time step in OPNET and VSS. Therefore, incorporating the HW-clock into the OPNET interface model would unnecessarily slow down the system-level simulation. In order to achieve a high simulation efficiency OPNET is chosen as master in our approach. Because zero messages are inserted at the VHDL interface model, the IPC overhead is reduced.