C-Compiler generation from LISA Processor Models
The progress in microprocessor technology has boosted the performance of general purpose desktop processors and embedded processors alike. This has two notable effects:
- Embedded processors are now with enough good performance to execute complex software.
- Customers now expect the features, programmable devices offer.
The increased complexity of the software is directly reflected in increased software development times and higher error rates. This effect is worsened by programming these processors at a very low abstraction level in assembly languages. Increasing the abstraction level of the programming level, for example by using a C compiler, is therefore desirable. However, development of a C compiler for an embedded processor is a time consuming task.
The LISA language, developed at RWTH-Aachen University from Synopsys, can be used to create a description of a microprocessor. This description can then serve as a golden model. This means that changes to the architechture need only be reflected in the LISA description. Other components like the HDL description, the software tools like the assembler and linker and a simulator for early software development are then automatically generated by the Processor Designer toolsuite from Synopsys.
The scope of this project is to add generation of a C compiler to the Processor Designer suite's capabilities. The main objectives are:
- Inclusion of C compilers in the processor architecture exploration loop
- Automatic generation of C compilers from LISA description
To generate a C compiler, Processor Designer utilizes the CoSy compiler development system from ACE. A brige has been created that connects the CoSy system to Processor Designer. It consists of two parts:
The first part is an automatic extraction of compiler-relevant features from the LISA description. The model is analyzed and details like the available registers, instructions and the calling conventions are automatically added to the compiler.
The second part is a graphical user interface which allows fine-tuning the compiler settings. This interface is tightly coupled to Processor Designer and allows the developer to fine tune the compiler's behaviour based on his expert knowledge of the architecture. At this level, several optimizations can also be added for different processor features like zero overhead loops.
The result of those two steps is a processor description which serves as input for the CoSy framework, to generate the final C compiler.