Advanced System Synthesis Tool
This new system-level synthesis technology is specifically targeted at coping with the exploding design complexity of modern digital communication systems. ASSET is an advanced RTL-HDL code generation that integrates high-level building blocks from different origins into a complete operable system-on-a-chip. Due to increases in ASIC design complexity, these building blocks reach a high level of functionality and have complex interfacing properties. These modules can be behavioral, RTL or gate-level modules. ASSET uses the dataflow description of communication systems created in COSSAP that have been mapped to cycle-based building blocks and automatically stitches together all the single components into a working system by generating additional interfaces and controlers.
As todays submicron chip technology rapidly emerges towards smaller structures, more and more functionality can be included on a single piece of silicon. In order to deal with the increasing complexity, a new ASIC design methodology is required. Designing a highly integrated IC from scratch, as it is presently practiced, results in a long time-to-market and requires a lot of expertise in both algorithm development and VLSI architectures.
Therefore, a shift in design paradigm is taking place towards combining high-level building blocks to design a complex system. Just as previously ICs of different functionality were plugged into a printed circuit board, LSI building blocks are now placed on a single chip (see ASSET logo).
These building blocks can be of different origin. First of all, existing components from previously designed systems can be reused. Furthermore, it will be possible to purchase building blocks from independent vendors of intellectual property (IP), which are already optimized regarding their functionality and architecture. In many systems it also necessary to design custom components needed for the specific application. The level of implementation of the single building blocks is not fixed either. They can be available at behavioral level, as synthesizable RTL-code, as a netlist of generic library components, as fully placed and routed netlists, or as full custom macros.
When applying the new building block based design methodology, much less time will be spent on the creation of the single building blocks, since most of them already exist. The most tedious and error prone design task is the integration of the single building blocks into a complete operable system.
Therefore, it becomes necessary to use advanced system design tools, which automate the generation of the additional interfaces and controllers required for system synthesis. This task can be performed efficiently using HDL code generation from data flow graphs.
Algorithm design is usually performed at a behavioral level using data flow oriented simulation tools like COSSAP. At this level of abstraction, simulation is very fast since the SDF model holds no notion of time. Therefore, the user can go through several quick simulations to evaluate the efficiency of the algorigthms. When the performance of the algorithms is satisfying, the purely functional SDF model of the system is mapped to the RTL target system architecture using RTL/HDL code generation. At this level of implementation the designer will do verification simulations, go through logic synthesis and get a cost estimation in terms of area, timing and power consumption.
This design methodology offers a seamless design flow since we are using the same specification for implementation as we used for synthesis. Furthermore, we are able to go through several design iterations quickly.
Now the question is, whether existing RTL/HDL code generation tools are capable of supporting the envisioned building block based design methodology. Let's have a look at the class of building blocks that these tools can handle. The following figure depicts the so called I/O-Pattern of a port of a building block that todays code generation tools are able to integrate. In the I/O pattern each box denotes a clock cycle in the processing phase of the corresponding building block. A shaded box implies that port access is taking place.
We can see that a fixed number of clock cycles elapses between each port access, which is equidistant port access. This, however, is a strong restriction concerning the building blocks we are allowed to use, as we will see in the following figure. Here, we depicted the input pattern of a multirate downsampling filter that was created using behavioral synthesis.
We can see that the filter component reads from its input data port with a certain periodicity and within that periodicity port access is non-equidistant. This behavior is typical for multirate building blocks that are used in todays ASIC designs. Conventional VHDL code generation tools do not support this non-equidistant I/O-pattern and therefore do not support the desired design flow.
In order to enable a building block based ASIC design methodology, we developed an advanced RTL-HDL code generation which is capable of integrating components with complex interfacing properties into a complete operable system. This tool is called ASSET.
Jens Horstmannshoff, Thorsten Grötker
Horstmannshoff, J. and Meyr, H.: Efficient Building Block Based RTL-HDL Code Generation from Synchonous Data Flow Graphs, in Proceedings of the Design Automation Conference (DAC) in Proceedings of the Design Automation Conference (DAC) , (Los Angeles) Jun/2000
Horstmannshoff, J. and Meyr, H.: Optimized System Synthesis of Complex RT Level Building Blocks, in Proceedings of the International Symposium on System Synthesis (ISSS) in Proceedings of the International Symposium on System Synthesis (ISSS) , (San Jose) Nov/1999
Horstmannshoff, J., Grötker, T., Meyr, H., Wloka, M. and Djigande, K.: DSP System Synthesis: Integration of Reusable Building Blocks, in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT) in Proc. Int. Conf. on Signal Processing Application and Technology (ICSPAT) , p.p. 774-778 , (San Diego) Sep/1997
Horstmannshoff, J., Grötker, T. and Meyr, H.: Mapping Multirate Dataflow to Complex RT Level Hardware Models, in ASAP in ASAP , IEEE, 1997