- Research
- Tools Projects
- Closed Projects
Closed Projects
- C-Compiler generation from LISA Processor Models
- LANCE C Compiler System
- Design Automation for ASIPs
- GRACE++ (NoC)
- Compilation and Architecture Exploration for Network Processors
- MPSoC Exploration
- HySim: Hybrid Simulation Framework
- Automated Implementation and Optimization of ASIPs
- SHAPES: Scalable Software Hardware Platform for Embedded Systems
- Software Washing Machine for Embedded Code
- FRIDGE
- ASSET
- Optimization for Retargetable Compilers
- OSIP: Operating System Application Specific Instruction Set Processor
- CoEx: Multi-Grained Level Application Profiler
- LISA-Compiler <--> Bus-Compiler Kopplung
- DSPstone
- LISA
- CASTANET
- SuperSim
- SPAM
- MPSoC debugging
- ASIP Instruction Set Extension Synthesis
- parSC – parallel SystemC
- Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)
- MIRA: Micro-Architectural Reliability Analysis for Deep Submicron Technology
- Advanced Coarse-grained Reconfigurable Architectures Design Methodology and Tools Research