Finished Projects

Advanced Coarse-grained Reconfigurable Architectures Design Methodology and Tools Research

Anupam Chattopadhyay, Zoltán Rákossy

C-Compiler generation from LISA Processor Models (SSS)

Manuel Hohenauer, Rainer Leupers

LANCE C Compiler System

Rainer Leupers

Design Automation for ASIPs

Juan Fernando Eusse

GRACE++ (NoC)

Torsten Kempf, Stefan Wallentowitz, Jens Reinecke, Andreas Wieferink, Tim Kogel, Andrea Kroll (Müllers), Guido Post, Malte Dörper, Christian Huben, Roland Nennen, Olaf Zerres

Compilation and Architecture Exploration for Network Processors (SSS)

Hanno Scharwächter

MPSoC Exploration

Torsten Kempf, Stefan Schürmans

HySim: Hybrid Simulation Framework (SSS)

Luis Gabriel Murillo, Jovana Jovic, Stefan Boßung (Kraemer), Lei Gao, Sergey Yakoushkin

Automated Implementation and Optimization of ASIPs

David Kammler, Anupam Chattopadhyay, Oliver Schliebusch

SHAPES: Scalable Software Hardware Platform for Embedded Systems (SSS)

Lei Gao, Stefan Boßung (Kraemer), Christoph Schumacher

Software Washing Machine for Embedded Code (SSS)

Stefan Boßung (Kraemer)

FRIDGE

ASSET

Jens Horstmannshoff, Thorsten Grötker

Optimization for Retargetable Compilers (SSS)

Felix Engel, Manuel Hohenauer, Maria Auras-Rodriguez, Sergey Yakoushkin

OSIP: Operating System Application Specific Instruction Set Processor

Jeronimo Castrillon, Diandian Zhang, Torsten Kempf

CoEx: Multi-Grained Level Application Profiler

Juan Fernando Eusse

LISA-Compiler <--> Bus-Compiler Kopplung

Andreas Wieferink, David Kammler

DSPstone

LISA

Anupam Chattopadhyay, Felix Engel, Manuel Hohenauer, David Kammler, Ernst Martin Witte, Gunnar Braun, Andreas Hoffmann, Tim Kogel, Achim Nohl, Andreas Ropers, Oliver Schliebusch, Oliver Wahlen, Andreas Wieferink

CASTANET

SuperSim

SPAM

MPSoC debugging

Luis Gabriel Murillo

ASIP Instruction Set Extension Synthesis

Juan Fernando Eusse, Jovana Jovic, Kingshuk Karuri

parSC – parallel SystemC

Christoph Schumacher, Jan Henrik Weinstock

Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)

Xiaolin Chen

MIRA: Micro-Architectural Reliability Analysis for Deep Submicron Technology

Zheng Wang, Anupam Chattopadhyay

News >> News >> News

ICE invites applications for a Postdoc position

Area: Application Specific Computing Systems and Hardware Architectures

EC selected TETRAMAX for funding, the successor of TETRACOM

We are glad to announce that the EC will grant the H2020 Innovation Action TETRAMAX with

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