EURETILE - EUropean REference TILed architecture Experiment
SSS is partner of the European FP7 Project EURETILE (EUropean REference TIled architecture Experiment), which has the goal to investigate and implement a brain-inspired massively parallel tiled computer architecture. The focus of SSS in EURETILE is the development of an efficient MPSoC simulation environment, which will be suitable for application development, software debugging and performance verification.
EURETILE is an EU project which aims at building an embedded massively parallel processing system. To manage this large number of hundreds of cores, the system hardware and software architecture is inspired by the construction of the human brain. By emulating three levels of the brain's connection hierarchy, namely, neural columns, cortical areas, and cortex, foundational innovations will lead to higher efficiency than traditional approaches while at the same time providing tolerance of faulty processing elements.
The basic architecture of EURETILE will build on the platform developed during the EU project SHAPES, which connected basic processing tiles in a toroidal 3D grid switched packet network. EURETILE enhances the connection network with additional capabilities for emulation of brain-like communication structures.
SSS Role in EURETILE
Our institute is in charge of the EURETILE full-system simulation environment. Since EURETILE systems comprise hundreds of cores, techniques that provide reasonable simulation speed are imperative. These techniques comprise: Abstract Simulation to execute part of the EURETILE application natively on the simulation host, as well as Parallel Simulation to spread simulation activity over a number of simulation host cores.
Furthermore, SSS is researching innovative debugging methodologies to support developers in efficiently analysing software malfunctions like race conditions, that are likely to appear and difficult to track in massively parallel systems.