Tool Flow and Architecture Exploration of reconfigurable ASIPs (rASIPs)

Motivation

Future wireless communication terminals tend to become multimode, multifunctional devices. The systems have to be cognitive to changing environmental conditions as well as adaptive to variable user demands. Flexibility now is becoming more important than ever. Considering the battery-served characteristic of wireless terminals, in order to support multiple modes and access technologies in future cognitive wireless systems, the required flexibility has to be achieved with an energy efficient implementation. Reconfigurable ASIPs (rASIPs), a new variant of ASIPs where custom processor components are mapped to a Coarse-Grained Reconfigurable Architecture (CGRA), represent a very promising architectural approach to meet both flexibility and energy requirements. Designing such a rASIP provides with a huge design space and therefore, is a challenging task. The goal of this project is to build up tool flow and use it for design space exploration and implementation of rASIPs.
 

Tool Flow

The integration of the tool flow with a commercial ADL-driven processor design framework is captured in the following figure. The software tool suite as well as the processor RTL description are automatically generated from the extended ADL description. The CGRA description is conceived as a part of the ADL LISA. For RTL implementation, recent advances in LISA-based tools also allow partitioning of the processor datapath to indicate if some part is going to be synthesized on to the CGRA. The partitioning results into a DFG description (of processor's partial datapath), which is fed directly as input to the CGRA synthesis tools (mapping, placement and routing tools). The CGRA synthesis flow generates configuration bitstream, which can be simulated on the HDL implementation of the CGRA. The simulation can be done stand-alone or together with the processor.

 

Architecture Exploration

The huge design space of rASIP (partly captured in the following figure) mainly comes from various design decisions on ASIP core architecture, reconfigurable block and the interface between them. In order to gain experience in the architectural development of rASIPs, which is a fairly new research topic, complex case studies need to be developed. Given the interest and experience of the institute in the domain of physical layer processing, the rASIP approach will be applied to critical algorithms for flexible receivers. One relevant research area for flexible receivers is MIMO de-mapping. rASIP can be used to implement a multi-mode MIMO detector supporting multiple de-mapping algorithms for multiple wireless communication standards.
 

Contact

Xiaolin Chen

Publications

Braun, G., Nohl, A., Sheng, W., Ceng, J., Hohenauer, M., Scharwächter, H., Leupers, R. and Meyr, H.: A novel approach for flexible and consistent ADL-driven ASIP design, in Design Automation Conference, p. 717, 2004


Kempf, T., Adrat, M., Witte, E. M., Ramakrishnan, V., Antweiler, M. and Ascheid, G.: On the Feasibility of Implementing a Waveform Application onto a Given SDR Platform, in Military CIS Conference 2006 (MCC2006) (formerly NATO RCMCIS)(Gdynia, Poland), Sep. 2006


Hadaschik, N., Zakia, I., Ascheid, G. and Meyr, H.: Joint narrowband interference detection and channel estimation for wideband OFDM, in Proceedings of the European Wireless Conference 2007(Paris, France), Apr. 2007


Wieferink, A., Meyr, H. and Leupers, R.: Retargetable Processor System Integration into Multi-Processor System-on-Chip Platforms, Springer, Jul. 2008, ISBN: 1-402-08574-5, 10.1007/978-1-4020-8652-6


Ramakrishnan, V., Veerkamp, T., Ascheid, G., Adrat, M. and Antweiler, M.: Implementations of Sorted-QR Decomposition for MIMO Receivers: Complexity, Reusability and Efficiency Analysis, in Springer Journal of Signal Processing Systems, Vol. 69, No. 1, pp. 41-53, Oct. 2012


Hohenauer, M., Engel, F., Leupers, R., Ascheid, G. and Meyr, H.: A SIMD Optimization Framework for Retargetable Compilers, 2009


Hadaschik, N.: Analysis of Wideband OFDM in the Presence of Narrowband Interference, Ph. D. Dissertation RWTH Aachen University, 2009


Jordan, M., Senst, M., Ascheid, G. and Meyr, H.: Long-Term Beamforming in Single Frequency Networks using Semidefinite Relaxation, in IEEE 67th Vehicular Technology Conference: VTC Spring 2008(Marina Bay, Singapore), in IEEE 67th Vehicular Technology Conference: VTC Spring 2008(Marina Bay, Singapore), May. 2008


Wang, Z., Chen, C. and Chattopadhyay, A.: Fast Reliability Exploration for Embedded Processors via High-level Fault Injection, in International Symposium on Quality Electronic Design (ISQED)(San Jose, CA, USA), pp. 265-272, 2013, ISBN: 978-1-46734-951-2, 10.1109/ISQED.2013.6523621


Colonna, A., Piscopiello, G., Errico, E., Tosi, P., Cordiviola, E., Bacci, B., Pii, V., Fanucci, L., Saponara, S., Donati, M., Vincenzi, A., Reiter, F., Nuzzolo, F., Leupers, R., Odendahl, M. and Yakoushkin, S.: DSPACE: A New Space DSP Development, in Proceedings of The International Space System Engineering Conference, May. 2012


Ishaque, A. and Ascheid, G.: I/Q Imbalance and CFO in OFDM/OQAM Systems: Interference Analysis and Compensation, in 24th Annual IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), 8-11 September, London, UK,, pp. 386-391, Sep. 2013, ISSN: 2166-9570, 10.1109/PIMRC.2013.6666166 ©2013 IEEE