Architecture

ICORE has a typical load-store 32 bit Harvard processor architecture with single instruction issue rate. The core currently implements about 60 DSP instructions. These instructions are subdivided into 18 arithmetic instructions, 14 instructions for program flow control including zero overhead loop instructions. The remaining instructions are used for memory and interface I/O operations, bit manipulations and logical operations etc. Furthermore, some highly optimized instructions support a fast CORDIC angle calculation.

ICORE uses a 3-stage pipeline:

  • FI: Fetch Instruction
  • ID: Instruction Decode
  • EX&WB: read operand/execute/write back

This short pipeline is advantageous for task with a high percentage of branch or jump instructions, because the branch penalty is very low.

ICORE uses 8 general purpose registers, 4 address register, a program counter and registers to support zero-overhead loop instructions. Dedicated functional units enable optimized instructions for bit manipulation and CORDIC computations etc.

Furthermore, the design entity in which ICORE is embedded contains:

  • 2048x20 instruction memory
  • 256x32 data memory
  • I2C registers (for the chip configuration)
  • dedicated I/O registers
  • test interface (to support chip test after fabrication)

The complete design including all the interfaces has been implemented using synthesizable VHDL within this project.

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