A low Power ASIP for DVB-T

    Project Summary

    Application Specific Instruction Set Processors (ASIPs) are the optimum architecture for heterogeneous, mixed  control-/data-flow oriented applications. ASIPs combine the flexibility of a programmable DSP with the efficiency and performance of dedicated hardware. Thus, ASIPs are the ideal architecture to optimize the trade-off between flexibility, performance and power consumption.

    In this project, the ICORE ASIP has been implemented. ICORE ( "ISS-CORE") is an ASIP, which implements all important acquisition and tracking tasks within a DVB-T receiver. This commercial DVB-T receiver has been designed in collaboration with an industry partner. The following picture shows the structure of the DVB-T receiver:


      The receiver is partitioned into dedicated hardware blocks with limited flexibility (like e. g. the FFT) and, on the other hand, into the ASIP block, which is realized by ICORE.