Flexible Implementation of Detection for MIMO-OFDM Receiver
Partially re-configurable ASIP (rASIP) is an important architecture which combines software flexibility and hardware configurability to match the needs of computational intensive and fast-evolving algorithms in wireless communication systems. In this project, the specific focus is on the applicability of rASIP technology to the design of a high-order flexible demapper supporting various configurations and algorithms for MIMO-OFDM receiver.
This project is closely related and contributes to the project "Tool Flow and Architecture Exploration of reconfigurable ASIPs". This project is mainly constructed by the following two parts.
The project will start with a study on existing linear and non-linear demapping algorithms with different antenna configurations and modulation schemes in MIMO-OFDM system. Within the project scope, some well-known as well as a few recently evolved sub-optimal demapping algorithms will be implemented. Comparisons will be done by analyzing the performance and implementation complexity among the different algorithms. The purpose of algorithm analysis is to figure out in which scenario these algorithms can be applied and how the targeted algorithms can be supported using rASIP technology. This knowledge is essential in the later hardware implementation stage to make design decisions for architecture exploration.
As the second step of the project, hardware exploration will be done in this stage. As a starting point of this stage, the implemented algorithms will be profiled on a configurable RISC core. For rASIP, a reconfigurable hardware accelerator needs to be extended to the RISC core in order to fulfill the high-order design constraints. Computation kernels can be figured out from the initial profiling result. Based on the profiling results and algorithm knowledge got from the former stage, design decisions for architecture exploration can be extracted. These design decisions may include, e.g. what features need to be extended at RISC core, which types of functional units and interconnects are needed inside reconfigurable accelerator in order to efficiently map the computation kernels onto it etc. Based on the design decisions, architecture exploration is performed.
This project is one of the first case studies being developed by applying rASIP technology on critical algorithms of physical layer processing. The implementation result can be compared directly with other approaches like, e.g. ASIC- and ASIP-based implementations. This comparison can give a first glance to evaluate in detail the pros and cons of rASIP as a next generation processing technology for MPSoCs.
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Fell, A., Rákossy, Z. E. and Chattopadhyay, A.: Force-Directed Scheduling for Data Flow Graph Mapping on Coarse-Grained Reconfigurable Architectures, in International Conference on ReConFigurable Computing and FPGAs (ReConFig)(Cancún, México), IEEE, Dec. 2014, 10.1109/ReConFig.2014.7032519 ©2014 IEEE