Architecture Projects

Power Estimation at Electronic System Level

Power consumption of chips is important, especially for mobile devices. To meet the low power requirements during the design of new chip, power consumption has be regarded already during early design space exploration. Unfortunately, classic power estimation tools operating on low levels are too time-consuming to permit this. A methodology for power estimation at Electronic System Level has been developed. It allows to create power models for existing ESL models. An evaluation of the methodology for modern communication architectures has shown that the estimation error is about 10% on average. For the ARM Cortex A9 processor, the methodology resulted in an estimation error of about 5% on average. An even smaller average estimation error of less than 4% has been shown in the Blackfin 609 DSP case study.

Optimization of 100 Gb/s near field wireless transmitters under consideration of power limits

This project is being conducted by Prof. Ascheid and Prof. Negra of RWTH Aachen together with Prof. Wehn of TU Kaiserslautern. This work is funded by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG).