Optimization of 100 Gb/s near field wireless transmitters under consideration of power limits
LP100: Optimization of 100 Gb/s near field wireless transmitters under consideration of power limits
This project is being conducted by Prof. Ascheid and Prof. Negra of RWTH Aachen together with Prof. Wehn of TU Kaiserslautern. This work is funded by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG).
Subject of this project is the scientific investigation of novel concepts for wireless short range transceivers operating at carrier frequencies of 60 GHz or 120 GHz and with a bandwidth between 1 and 10 GHz. A particular processing-energy per information bit, leads to a power consumption increasing with the data rate. For data rates in the order of 100 Gb/s, the power consumption of the transceiver will increase significantly. Therefore, in this project transceivers will be optimized for maximum throughput, while taking the energy constraints into consideration. Consequently, transmit- and processing-energy will be considered on a per-information-bit basis. In order to achieve the objectives, we will study suitable radio-frequency (RF) architectures and transmission schemes, jointly with energy-efficient architectures and their implementation in a real cross layer approach. Major challenges are in the approaches to achieve transmission rates in the order of 100 Gb/s and in an analog/digital partitioning of the signal processing tasks that supports the data rates but stays within acceptable limits for the consumed energy per information bit.
Guo, K., Dai, S., Zhang, C., Fodor, G. and Ascheid, G.: Massive MIMO Aided Multi-Pair Relaying with Underlaid D2D Communications, in Proceedings of European Wireless Conference (EW), pp. 399-404, VDE, May. 2017, ISBN: 978-3-80074-426-8
Wang, G., Naeimi, S. A. and Ascheid, G.: Low Complexity Channel Estimation Based on DFT for Short Range Communication, in Proceedings of IEEE International Conference on Communications (ICC), pp. 1-7, May. 2017, 10.1109/ICC.2017.7996917 ©2017 IEEE
Wang, G., Bytyn, A., Khajavi , D., Wang, Y., Negra, R. and Ascheid, G.: Power Efficiency of Millimeter Wave Transmission Systems with Large Number of Antennas, in Proceedings of IEEE Vehicular Technology Conference (VTC-Fall), pp. 1-6, Sep. 2016 ©2016 IEEE
Schürmans, S., Führ (Onnebrink), G., Leupers, R., Ascheid, G. and Chen, X.: ESL Power Estimation using Virtual Platforms with Black Box Processor Models, in ViPES Workshop 2015, pp. 354 - 359, Jul. 2015, 10.1109/SAMOS.2015.7363698
Wang, G., karanjekar, P. and Ascheid, G.: Beamforming with Time-Delay Compensation for 60 GHz MIMO Frequency-Selective Channels, in Proceedings of IEEE International Symposium on Personal, Indoor, and Mobile Radio Communications (PIMRC), Aug. 2015, 10.1109/PIMRC.2015.7343329 ©2015 IEEE
Eusse, J. F., Williams, C. and Leupers, R.: CoEx: A Novel Profiling-Based Algorithm/Architecture Co-Exploration for ASIP Design, in ACM Transactions on Reconfigurable Technology and Systems, May. 2014, 10.1109/ReCoSoC.2013.6581520
The key objectives of this project thus lie in the design of innovative RF, mixed-signal, and digital signal processing architectures to achieve high power efficiency, bandwidth efficiency and implementation efficiency for ultra-high data rates. To achieve the key objectives a number of major topics has to be studied, namely realization of high modulation orders, many-antenna transmission, partitioning into analog and digital signal processing, digitally adjusted/switched analog processing, compensation of the influence of hardware imperfections on the signal, and energy efficient silicon implementation. For all concepts, their impact on the throughput and their contribution to the total energy consumption will be key parameters. Thus, energy/power estimation and budgeting is a final key topic of the projects research.
After researching system architectures for 60 GHz and power-efficient implementation of the digital signal processing in the first phase, in the second phase critical components will be implemented and their performance will be compared to the behavior, which was determined by theoretical analysis and by simulation. In parallel, power-optimized system architectures for the 120 GHz range (and beyond) will be studied and, thus, also the power consumption based design space exploration method, which has been developed in the first phase, will be verified. A demonstrator will be developed by a fabricated RF chip. Critical components of the digital baseband processing will be implemented e.g. on FPGAs to evaluate the proposed algorithms for the system architecture in a mm-wave transmission scenario.
There are close interrelations between the requirements on high frequency, mixed signal and digital side from a communications and implementation point of view. The intensive interdisciplinary collaboration of researchers from the different fields is therefore essential to achieve the ambitious goals.