Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

Multi-Grained Performance Estimation for MPSoC Compilers

Authors:: Aguilar, M. A. , Aggarwal, A. , Shaheen, A. , Leupers, R. , Ascheid, G. , Castrillon, J. , Fitzpatrick, L.
Book Title:: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)
Publisher:: ACM
Pages:: p.p. 14:1-14:2
Address:: Seoul, Republic of Korea
Date:: Oct. 2017
ISBN:: 978-1-45035-184-3
DOI:: 10.1145/3125501.3125521
hsb:: RWTH-2018-00020
Language:: English
Abstract:: Parallelizing compilers are a promising solution to tackle key challenges of MPSoC programming. One fundamental aspect for a profitable parallelization is to estimate the performance of the applications on the target platforms. There is a wide range of state-of-the-art performance estimation techniques, such as, simulation-based, measurement-based, among others. They provide performance estimates typically only at function or basic block granularity. However, MPSoC compilers require performance information at other granularities, such as statement, loop or even arbitrary code blocks. In this paper, we propose a framework to adapt performance information sources to any granularity required by an MPSoC compiler.
Download:: BibTeX