Sie verwenden einen Browser, in dem JavaScript deaktiviert ist. Dadurch wird verhindert, dass Sie die volle Funktionalität dieser Webseite nutzen können. Zur Navigation müssen Sie daher die Sitemap nutzen.

You are currently using a browser with deactivated JavaScript. There you can't use all the features of this website. In order to navigate the site, please use the Sitemap .

Parallel SystemC Simulation for ESL Design using Flexible Time Decoupling

Authors:: Weinstock, J. H. , Leupers, R. , Ascheid, G.
Book Title:: Proceedings of the Workshop on Virtual Prototyping of Parallel and Embedded Systems (VIPES 2015)
Pages:: p.p. 378 - 383
Address:: Samos, Greece
Date:: Jul. 2015
ISBN:: 978-1-46737-311-1
DOI:: 10.1109/SAMOS.2015.7363702
Language:: English
Abstract:: Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious.
Recently published parallel SystemC simulators use time-decoupling to achieve high simulation performance on modern SMP machines. However, those simulators have to identify all cross-thread communication ahead of time. This work presents an approach how to overcome this limitation and to enable time-decoupled simulation for mainstream SystemC simulators, achieving a speedup of up to 3.4x on a quad-core host.
Download:: BibTeX