Institute for Communication Technologies and Embedded Systems

Efficient VLSI Architectures for Matrix Inversion in Soft-Input Soft-Output MMSE MIMO Detectors

Authors:
Auras, D.Leupers, R.Ascheid, G.
Book Title:
Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
Pages:
p.p. 1018 - 1021
Date:
Jun. 2014
ISBN:
978-1-47993-431-7
DOI:
10.1109/ISCAS.2014.6865311
Language:
English
Abstract:
A computational complexity analysis of matrix inversion used in soft-input soft-output minimum mean square error (MMSE) MIMO detectors and a comprehensive literature comparison of corresponding VLSI implementations are presented. They indicate that the application specific integrated circuit (ASIC) proposed in this paper is — to the best of our knowledge — the most area-throughput efficient VLSI architecture reported so far, outperforming the second best by a factor of 1.7x. The ASIC achieves the IEEE 802.11n standard’s peak data rate of 600 Mbit/s.
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