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A 2.78 mm² 65 nm CMOS Gigabit MIMO Iterative Detection and Decoding Receiver

Authors:: Borlenghi, F. , Witte, E. M. , Ascheid, G. , Meyr, H. , Burg, A.
Book Title:: IEEE European Solid-State Circuits Conference (ESSCIRC)
Date:: Sep. 2012
DOI:: 10.1109/ESSCIRC.2012.6341257
Language:: English
Abstract:: Iterative detection and decoding (IDD), combined with spatial-multiplexing multiple-input multiple-output (MIMO) transmission, is a key technique to improve spectral efficiency in wireless communications. In this paper we present the - to the best of our knowledge - first complete silicon implementation of a MIMO IDD receiver. MIMO detection is performed by a multi-core sphere decoder supporting up to 4×4 as antenna configuration and 64-QAM modulation. A flexible low-density parity check decoder is used for forward error correction. The 65nm CMOS ASIC has a core area of 2.78 mm2. Its maximum throughput exceeds 1 Gbit/s, at less than 1nJ/bit. The MIMO IDD ASIC enables more than 2 dB performance gains with respect to non-iterative receivers.
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