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Just-in-Time Verification in ADL-based Processor Design

Authors:: Auras, D. , Minwegen, A. , Deidersen, U. , Schürmans, S. , Ascheid, G. , Leupers, R.
Book Title:: SAMOS XII: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation
Pages:: p.p. 1 - 6
Address:: Samos, Greece
Date:: Jul. 2012
ISBN:: 978-1-46732-296-6
DOI:: 10.1109/SAMOS.2012.6404151
Language:: English
Abstract:: A novel verification methodology, combining the two new techniques of Live Verification and Processor State Transfer, is introduced to Architecture Description Language (ADL) based processor design. The proposed Just-in-Time Verification significantly accelerates the simulation-based equivalence check of the register-transfer and instruction-set level models, generated from the ADL-based specification. This is accomplished by omit- ting redundant simulation steps occurring in the conventional architecture debug cycle. The potential speedup is demonstrated with a case study, achieving an acceleration of the debug cycle by 660x.
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