Institute for Communication Technologies and Embedded Systems

logo: Institute for Communication Technologies and Embedded Systems

Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis

Authors:
Zhang, D. ,  Zhang, H. ,  Castrillon, J. ,  Kempf, T. ,  Vanthournout, B. ,  Ascheid, G. ,  Leupers, R.
Journal:
(IJERTCS)
Volume:
2
Page(s):
1-20
number:
3
Date:
2011
DOI:
10.4018/jertcs.2011070101
Language:
English
Abstract:
Efficient runtime resource management in multi-processor systems-on-chip (MPSoCs) for achieving high performance and low energy consumption is one of the key challenges for system designers. OSIP, an operating system application-specific instruction-set processor, together with its well-defined programming model, provides a promising solution to this. It delivers high computational performance to deal with dynamic task scheduling and mapping. Being programmable, it can easily be adapted to different systems. However, the distributed computation among the different processing elements introduces complexity to the communication architecture, which tends to become the bottleneck of such systems. In this work, we highlight the vital importance of the communication architecture for OSIP-based systems and optimize the communication architecture. Furthermore, we investigate the effects of OSIP and the communication architecture jointly from the system point of view, based on a broad case study for a real life application (H.264) and a synthetic benchmark application.
Download:
BibTeX