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A Processor-Level NBTI Mitigation Technique of Applying Anti-Aging Gate Control through Instruction Set Architecture

Authors:: Song, B. , Michihiro, S. , Wang, Z. , Masayuki, H. , Chattopadhyay, A. , Takashi, S.
Book Title:: In IEICE Conference of VLSI Design Technologies (VLD)
Publisher:: IEICE
Pages:: p.p. 49-54
Address:: Okinawa Prefecture, Japan
Date:: Mar. 2015
Language:: English
Abstract:: As the technology process of transistors becomes yet smaller, Negative Bias Temperature Instability (NBTI) has became one of the major threat to the performance and reliability of modern digital circuits. In this research, we propose a technique to mitigate the NBTI aging effect in processors by utilizing the NOP instruction to support a hardware-level modification. First, vectorless probability analysis is applied to each gate in the critical paths, and NBTI-stressed gates are identified. Second, specially-crafted gates are inserted to the upstream of stressed gates. Finally, the healing functionality of the inserted special gates are initiated by the NOP instruction, and the downstream gates are then healed. The proposed technique was applied to an example five-stage pipelined processor. Simulation results indicate that our method achieved about 12.5% improvement in the worst-case path delay in a 10-year span with only a small amount of area and power overheads.
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