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High-level Modeling, Estimation and Exploration of Reliability for MPSoC

Authors:: Wang, Z.
Date:: 2015
DOI:: 10.1109/IWCIT.2015.7140217
Language:: English
Abstract:: A key ingredient of successful cross-layer exploration of reliability against other performance constraints (e.g. power, temperature, speed) is to accurately model the faults prevalent in deep sub-micron technologies and develop a smooth tool flow at high-level design platform to analyze the effect of such faults. In this thesis, we are tackling multiple challenges for developing the reliability-estimation and exploration framework.
Download:: BibTeX