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Processor Design with Asymmetric Reliability

Authors:: Wang, Z. , Paul, G. , Chattopadhyay, A.
Book Title:: IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Series:: IEEE Computer Society Annual Symposium on VLSI
Pages:: p.p. 565 - 570
Address:: Tampa, Florida, USA
Date:: Jul. 2014
DOI:: 10.1109/ISVLSI.2014.63
Language:: English
Abstract:: Continuous shrinking of device size has introduced reliability as a new challenge for improving design lifetime, mitigating errors and allowing various performance trade-offs. Reliability is a cross-layer design issue, where errors need to be managed starting from the algorithm down to the circuit. To facilitate such a design, we adopt an information-theoretic view of embedded processors, where the processor is conceptualized as a noisy network. We propose a versatile asymmetric error detection/correction framework based on instruction-level vulnerability analysis. To efficiently trade-off reliability with other performance constraints, multiple novel techniques are proposed, which are evaluated through a range of experiments.
Download:: BibTeX