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Deceptive Logic Locking for Hardware Integrity Protection against Machine Learning Attacks

Authors:: Šišejković, D. , Merchant, F. , Reimann, L. M. , Leupers, R.
Journal:: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)
Date:: Jul. 2021
ISSN:: 1937-4151
DOI:: 10.1109/TCAD.2021.3100275
hsb:: RWTH-2021-11818
Language:: English
Abstract:: Logic locking has emerged as a prominent key-driven technique to protect the integrity of integrated circuits. However, novel machine-learning-based attacks have recently been introduced to challenge the security foundations of locking schemes. These attacks are able to recover a significant percentage of the key without having access to an activated circuit. This paper address this issue through two focal points. First, we present a theoretical model to test locking schemes for key-related structural leakage that can be exploited by machine learning. Second, based on the theoretical model, we introduce D-MUX: a deceptive multiplexer-based logic-locking scheme that is resilient against structure-exploiting machine learning attacks.Through the design of D-MUX, we uncover a major fallacy in existing multiplexer-based locking schemes in the form of a structural-analysis attack. Finally, an extensive cost evaluation of D-MUX is presented.To the best of our knowledge, D-MUX is the first machine-learning-resilient locking scheme capable of protecting against all known learning-based attacks. Hereby, the presented work offers a starting point for the design and evaluation of future-generation logic locking in the era of machine learning.
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