Publication: Protecting the Integrity of Processor Cores with Logic Encryption 

Authors:
Šišejković, D.Merchant, F.Leupers, R.
Book Title:
2019 32nd IEEE International System-on-Chip Conference (SOCC)
Pages:
p.p. 424-425
Date:
2019
DOI:
10.1109/SOCC46988.2019.1570564157
hsb:
RWTH-2021-00467
Language:
English

Abstract

Malicious circuit modifications known as hardware Trojans represent a rising threat to the integrated circuit supply chain. Logic encryption has emerged as a prominent technique for protecting the integrity of circuit designs. In recent years, an extensive amount of logic encryption algorithms have been introduced. However, existing approaches focus on isolated circuit components without considering the modularity and complexity of modern hardware designs. In this work, we focus on several aspects of protecting modern processor core designs. Firstly, we discuss Inter-Lock, a novel approach to scaling logic encryption to multi-module hardware designs by leveraging inter-module dependencies. Inter-Lock is efficiently able to exponentially increase the security and render attacks on isolated modules infeasible by undermining the basic assumption that the key inputs are known. Secondly, we present Control-Lock, a methodology for protecting critical inter-module control signals in hardware designs against software-controlled hardware Trojans. Both techniques are evaluated on a RISC-V processor core with respect to the area, delay and power overhead. Lastly, we briefly discuss a unifying logic encryption metric as well as acceptable overheads for widely used benchmarks.

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