Publication: Inter-Lock: Logic Encryption for Processor Cores Beyond Module Boundaries 

Authors:
Šišejković, D.Merchant, F.Leupers, R.Ascheid, G. ,  Kegreiß, S.
Book Title:
2019 IEEE European Test Symposium (ETS)
Pages:
p.p. 1-6
Date:
May. 2019
ISSN:
1530-1877
DOI:
10.1109/ETS.2019.8791528
hsb:
RWTH-2020-00052
Language:
English

Abstract

The lack of technical resources and the high cost of establishing a semiconductor foundry has forced most integrated circuit design houses to rely on outsourcing part of their design and fabrication services to off-site companies. The involvement of external parties has given rise to major security threats, ranging from intellectual property piracy to the insertion of malicious circuits. Logic encryption has emerged as a popular mitigation technique against these threats. In recent years, a vast amount of logic encryption algorithms has been proposed. However, existing approaches strongly focus on isolated circuit components without taking the complexity and modular structure of modern circuit designs into account. In this paper, we propose Inter-Lock, a novel logic encryption framework tailored towards scaling logic encryption to larger designs by leveraging their complexity and exploiting multi-module interdependencies to exponentially enhance the security of sequential circuits. To showcase the applicability of the approach, we present an extensive evaluation on a real-life 32-bit RISC-V core together with the analysis of the security-cost trade-off. Our recommended Inter-Lock configuration of the core features a 1024-bit key and 100% functional corruption for 13.2% area overhead, less than 1% power overhead and 22.2% delay penalty in the worst case.

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